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CXD3029R データシート(PDF) 55 Page - Sony Corporation

部品番号 CXD3029R
部品情報  CD Digital Signal Processor with Built-in Digital Servo Shock-proof Memory Controller Digital High & Bass Boost
Download  201 Pages
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メーカー  SONY [Sony Corporation]
ホームページ  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD3029R データシート(HTML) 55 Page - Sony Corporation

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CXD3029R
When SLDBBIN = 0, the internally connected data is selected. (default)
DTSL1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
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0
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DSP mode
Shock-proof
memory controller
mode
DSP mode
Shock-proof
memory controller
mode
DSP mode
Shock-proof
memory controller
mode
DSP mode
Shock-proof
memory controller
mode
DSP & DAC mode
Shock-proof
memory controller
& DAC mode
DSP mode
Shock-proof
memory controller
mode
DSP mode
External mode
DSP mode
DSP & DAC mode
Shock-proof memory
controller mode
Shock-proof memory
controller & DAC mode
DSP mode
DSP & DAC mode
Shock-proof memory
controller mode
Shock-proof memory
controller & DAC mode
DSP mode
DSP & DAC mode
Shock-proof memory
controller mode
Shock-proof memory
controller & DAC mode
DSP mode
DSP & DAC mode
Shock-proof memory
controller mode
Shock-proof memory
controller & DAC mode
DTSL0 SDSL2 SDSL1 SDSL0 Input to DAC block
DOUT output
PCMD output
∗: preset
1: The relationship between LRCK, BCK and PCMD changes according to the setting value.
When SDSL0 = 0, the LRCK, BCK and PCMD phase difference is constant but the LRCK frequency
changes when SDSL0 is switched.
When SDSL0 = 1, the LRCK frequency is constant but the phase difference between LRCK, BCK and
PCMD changes before and after SDSL1 is switched. When not switching the output data selection, set
SDSL1 and SDSL0 to the same value.
max C2PO7 to max C2PO0:
These bits set the C2PO conditions.
max C2PO7 to max C2PO0
Processing
The C2PO upper limit value reflected to mon C2PO and
added to the write prohibited condition.
00000000 to 11111111


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