© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FIN424C / FIN425C • Rev. 1.0.0

5

STRB

DP[17:0]

DP[18]

DP[19]

/RES

/STBY

Test

CKS+

CKS-

DS+

DS-

VDDP VDDS/A

/WE

DP[17:0]

A0

CS

Reset

/STBY

Baseband

Processor

GND

CKS+

CKS-

DS+

DS-

GND

Main Display

18-Bit µController

/WE

DATA[17:0]

/A0

CS

RESET

VDDP VDDS/A

FIN424C

FIN425C

1.8V

2.8V

WCLK

DP[17:0]

DP[18]

DP[19]

Slew

Test

/RES

2.8V

2.8V

-

-

-

-

-

Figure 5.

Single–Display, 18-Bit, µController Interface

STRB

DP[17:0]

DP[18]

DP[19]

/RES

/STBY

Test

CKS+

CKS-

DS+

DS-

VDDP VDDS/A

PCLK

DP[17:0]

HSYNC

VSYNC

/CS

Reset

/STBY

Baseband

Processor

GND

CKS+

CKS-

DS+

DS-

GND

Main Display

18-Bit RGB

PCLK

DATA[17:0]

HSYNC

VSYNC

/CS

RESET

VDDP VDDS/A

FIN424C

FIN425C

1.8V

2.8V

WCLK

DP[17:0]

DP[18]

DP[19]

Slew

Test

/RES

2.8V

2.8V

-

-

-

-

-

Figure 6.

Single-Display, 18-Bit, RGB Interface

Additional Application Information

Flex Cabling:

The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O

flex cable. The following best practices should be used when developing the flex cabling or Flex PCB.

Keep all four differential serial wires the same length.

Do not allow noisy signals over or near differential serial wires. Example: No CMOS traces over differential serial wires.

Use a design goal of 70 to 130

Ω differential characteristic impedance.

Do not place test points on differential serial wires.

Design differential serial wires a minimum of 2cm away from the antenna.