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FDD6N50TM データシート(PDF) 1 Page - Fairchild Semiconductor |
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FDD6N50TM データシート(HTML) 1 Page - Fairchild Semiconductor |
1 / 8 page ©20 10 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDD6N50 TM_F085 Rev. C1 FDD6N50TM_F085 500V N-Channel MOSFET Features • 6A, 500V, RDS(on) = 0.9Ω @VGS = 10 V • Low gate charge ( typical 12.8 nC) •Low Crss ( typical 9 pF) Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficient switched mode power supplies and active power factor correction. D-PAK GS D D G S Absolute Maximum Ratings Symbol Parameter Ratings Unit VDSS Drain-Source Voltage 500 V ID Drain Current - Continuous (TC = 25°C) - Continuous (TC = 100°C) 6 3.8 A A IDM Drain Current - Pulsed (Note 1) 24 A VGSS Gate-Source voltage ±30 V EAS Single Pulsed Avalanche Energy (Note 2) 270 mJ IAR Avalanche Current (Note 1) 6 A EAR Repetitive Avalanche Energy (Note 1) 8.9 mJ dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns PD Power Dissipation (TC = 25°C) - Derate above 25 °C 89 0.71 W W/ °C TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C TL Maximum Lead Temperature for Soldering Purpose, 1/8” from Case for 5 Seconds 300 °C Thermal Characteristics Symbol Parameter Min. Max. Unit RθJC Thermal Resistance, Junction-to-Case -- 1.4 °C/W RθJA Thermal Resistance, Junction-to-Ambient -- 83 °C/W • 100% avalanche tested • Improved dv/dt capability •Fast switching •RoHS Compliant • Qualified to AEC Q101 Novemb er 2010 |
同様の部品番号 - FDD6N50TM_10 |
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同様の説明 - FDD6N50TM_10 |
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