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74LVTH574WM データシート(PDF) 2 Page - Fairchild Semiconductor

部品番号 74LVTH574WM
部品情報  Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74LVTH574WM データシート(HTML) 2 Page - Fairchild Semiconductor

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©1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVT574, 74LVTH574 Rev. 1.6.0
2
Connection Diagram
Pin Description
Functional Description
The LVT574 and LVTH574 consist of eight edge-
triggered flip-flops with individual D-type inputs and
3-STATE true outputs. The buffered clock and buffered
Output Enable are common to all flip-flops. The eight
flip-flops will store the state of their individual D-type
inputs that meet the setup and hold time requirements
on the LOW-to-HIGH Clock (CP) transition. With the Out-
put Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When the OE is HIGH, the
outputs go to the high impedance state. Operation of the
OE input does not affect the state of the flip-flops.
Logic Symbols
IEEE/IEC
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
= LOW-to-HIGH Transition
Oo = Previous Oo before HIGH to LOW of CP
Pin Names
Description
D0–D7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Outputs
Inputs
Outputs
Dn
CP
OE
On
HL
H
LL
L
XL
L
Oo
XX
H
Z


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