©1997 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74VHCT573A Rev. 1.3

2

Logic Symbol

IEEE/IEC

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

Z

= High Impedance

Functional Description

The VHCT573A contains eight D-type latches with

3-STATE output buffers. When the Latch Enable (LE)

In this condition the latches are transparent, i.e., a latch

output will change state each time its D input changes.

When LE is LOW the latches store the information that

was present on the D inputs, a setup time preceding the

HIGH-to-LOW transition of LE. The 3-STATE buffers are

controlled by the Output Enable (OE) input. When OE is

LOW, the buffers are enabled. When OE is HIGH the

buffers are in the high impedance mode, but, this does

not interfere with entering new data into the latches.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

Inputs

Outputs

OE

LE

D

LH

H

H

LHL

L

LL

X

HX

X

Z