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FM22LD16 データシート(PDF) 5 Page - Cypress Semiconductor |
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FM22LD16 データシート(HTML) 5 Page - Cypress Semiconductor |
5 / 14 page FM22LD16 - 256Kx16 FRAM Rev. 3.0 Oct. 2012 Page 5 of 14 along with a new column address provides a page mode write access. Precharge Operation The precharge operation is an internal condition in which the state of the memory is being prepared for a new access. Precharge is user-initiated by driving the /CE signal high. It must remain high for at least the minimum precharge time tPC. Precharge is also activated by changing the upper addess A(17:2). The current row is first closed prior to accessing the new row. The device automatically detects an upper order address change which starts a precharge operation, the new address is latched, and the new read data is valid within the tAA address access time. Refer to the Read Cycle Timing 1 diagram on page 10. Likewise a similar sequence occurs for write cycles. Refer to the Write Cycle Timing 3 diagram on page 12. The rate at which random addresses can be issued is tRC and tWC, respectively. Software Write Protection The 256Kx16 address space is divided into 8 sectors (blocks) of 32Kx16 each. Each sector can be individually software write-protected and the settings are nonvolatile. A unique address and command sequence invokes the write protection mode. To modify write protection, the system host must issue six read commands, three write commands, and a final read command. The specific sequence of read addresses must be provided in order to access to the write protect mode. Following the read address sequence, the host must write a data byte that specifies the desired protection state of each sector. For confirmation, the system must then write the complement of the protection byte immediately following the protection byte. Any error that occurs including read addresses in the wrong order, issuing a seventh read address, or failing to complement the protection value will leave the write protection unchanged. The write protect state machine monitors all addresses, taking no action until this particular read/write sequence occurs. During the address sequence, each read will occur as a valid operation and data from the corresponding addresses will be driven onto the data bus. Any address that occurs out of sequence will cause the software protection state machine to start over. After the address sequence is completed, the next operation must be a write cycle. The data byte contains the write-protect settings. This value will not be written to the memory array, so the address is a don’t-care. Rather it will be held pending the next cycle, which must be a write of the data complement to the protection settings. If the complement is correct, the write protect settings will be adjusted. If not, the process is aborted and the address sequence starts over. The data value written after the correct six addresses will not be entered into memory. The protection data byte consists of 8-bits, each associated with the write protect state of a sector. The data byte must be driven to the lower 8-bits of the data bus, DQ(7:0). Setting a bit to 1 write protects the corresponding sector; a 0 enables writes for that sector. The following table shows the write-protect sectors with the corresponding bit that controls the write-protect setting. Write Protect Sectors – 32K x16 blocks Sector 7 3FFFFh – 38000h Sector 6 37FFFh – 30000h Sector 5 2FFFFh – 28000h Sector 4 27FFFh – 20000h Sector 3 1FFFFh – 18000h Sector 2 17FFFh – 10000h Sector 1 0FFFFh – 08000h Sector 0 07FFFh – 00000h The write-protect read address sequence follows: 1. 24555h * 2. 3AAAAh 3. 02333h 4. 1CCCCh 5. 000FFh 6. 3EF00h 7. 3AAAAh 8. 1CCCCh 9. 0FF00h 10. 00000h * If /CE is low entering the sequence, then an address of 00000h must precede 24555h. The address sequence provides a very secure way of modifying the protection. The write-protect sequence has a 1 in 3 x 10 32 chance of randomly accessing exactly the 1 st six addresses. The odds are further reduced by requiring three more write cycles, one that requires an exact inversion of the data byte. A flow chart of the entire write protect operation is shown in Figure 2. The write-protect settings are nonvolatile. The factory default: all blocks are unprotected. |
同様の部品番号 - FM22LD16 |
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同様の説明 - FM22LD16 |
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