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FM22LD16-55-BGTR データシート(PDF) 10 Page - Cypress Semiconductor

部品番号 FM22LD16-55-BGTR
部品情報  4Mbit F-RAM Memory
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM22LD16-55-BGTR データシート(HTML) 10 Page - Cypress Semiconductor

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FM22LD16 - 256Kx16 FRAM
Rev. 3.0
Oct. 2012
Page 10 of 14
Power Cycle Timing (TA = -40 C to + 85 C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Notes
tPU
Power-Up (after VDD min. is reached) to First Access Time
450
-
s
tPD
Last Write (/WE high) to Power Down Time
0
-
s
tVR
VDD Rise Time
50
-
s/V
1,2
tVF
VDD Fall Time
100
-
s/V
1,2
Notes
1
Slope measured at any point on VDD waveform.
2
Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict
when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than
100ms through the range of 0.4V to 1.0V.
Data Retention (VDD = 2.7V to 3.6V)
Parameter
Min
Units
Notes
Data Retention
10
Years
AC Test Conditions
Input Pulse Levels
0 to 3V
Input and Output Timing Levels
1.5V
Input Rise and Fall Times
3 ns
Output Load Capacitance
30pF
Read Cycle Timing 1 (/CE low, /OE low)
A(17:0)
tRC
tAA
Previous Data
Valid Data
tOH
Valid Data
tRC
tAA
tOH
DQ(15:0)
Read Cycle Timing 2 (/CE-controlled)
A(17:0)
DQ(15:0)
tAS
tHZ
tOE
tOH
tOHZ
UB / LB
OE
CE
tBA
tBHZ
tCA
tPC
tAH
tCE


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