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FM23MLD16 データシート(PDF) 7 Page - Cypress Semiconductor

部品番号 FM23MLD16
部品情報  8Mbit F-RAM Memory
Download  13 Pages
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM23MLD16 データシート(HTML) 7 Page - Cypress Semiconductor

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FM23MLD16 - 512Kx16 FRAM (multi die)
Rev. 2.0
June 2012
Page 7 of 13
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
Ratings
VDD
Power Supply Voltage with respect to VSS
-1.0V to +4.5V
VIN
Voltage on any signal pin with respect to VSS
-1.0V to +4.5V and
VIN < VDD+1V
TSTG
Storage Temperature
-55
°C to +125°C
TLEAD
Lead Temperature (Soldering, 10 seconds)
300
° C
VESD
Electrostatic Discharge Voltage
- Human Body Model (JEDEC Std JESD22-A114-D)
- Charged Device Model (JEDEC Std JESD22-C101-C)
- Machine Model (JEDEC Std JESD22-A115-A)
1.5kV
1.2kV
170V
Package Moisture Sensitivity Level
MSL-3
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
Notes
VDD
Power Supply
2.7
3.3
3.6
V
IDD
Power Supply Current
9
14
mA
1
ISB
Standby Current
@ TA = 25°C
@ TA = 85°C
180
-
300
540
μA
μA
2
VTP
VDD Trip Point to Block Accesses
2.2
-
2.6
V
3
ILI
Input Leakage Current
±1
μA
ILO
Output Leakage Current
±1
μA
VIH
Input High Voltage
2.2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.6
V
VOH1
Output High Voltage (IOH = -1.0 mA)
2.4
V
VOH2
Output High Voltage (IOH = -100 μA)
VDD-0.2
V
VOL1
Output Low Voltage (IOL = 2.1 mA)
0.4
V
VOL2
Output Low Voltage (IOL = 100 μA)
0.2
V
Notes
1.
VDD = 3.6V, CE pin(s) cycling at min. cycle time. All inputs toggling at CMOS levels (0.2V or VDD-0.2V), all DQ pins
unloaded.
2.
VDD = 3.6V, /CE1 at VDD or CE2 at VSS, all other pins are static and at CMOS levels (0.2V or VDD-0.2V).
3.
If VDD < VTP, all memory accesses are blocked regardless of input pin conditions.


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