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FM24C16B-GTR データシート(PDF) 8 Page - Cypress Semiconductor

部品番号 FM24C16B-GTR
部品情報  16Kb Serial 5V F-RAM Memory
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM24C16B-GTR データシート(HTML) 8 Page - Cypress Semiconductor

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FM24C16B - 16Kb 5V I2C F-RAM
Rev. 3.0
Jan. 2012
Page 8 of 12
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
Ratings
VDD
Power Supply Voltage with respect to VSS
-1.0V to +7.0V
VIN
Voltage on any signal pin with respect to VSS
-1.0V to +7.0V
and VIN < VDD+1.0V *
TSTG
Storage Temperature
-55C to +125C
TLEAD
Lead Temperature (Soldering, 10 seconds)
260 C
VESD
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
4kV
1.25kV
100V
Package Moisture Sensitivity Level
MSL-1
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of
this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device
reliability.
DC Operating Conditions (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
Notes
VDD
Main Power Supply
4.5
5.0
5.5
V
IDD
VDD Supply Current
@ SCL = 100 kHz
@ SCL = 400 kHz
@ SCL = 1 MHz
100
200
400
A
A
A
1
ISB
Standby Current
4
10
A
2
ILI
Input Leakage Current
±1
A
3
ILO
Output Leakage Current
±1
A
3
VIL
Input Low Voltage
-0.3
0.3 VDD
V
VIH
Input High Voltage
0.7 VDD
VDD + 0.3
V
VOL
Output Low Voltage
@ IOL = 3 mA
0.4
V
RIN
Input Resistance (WP pin)
For VIN = VIL (max)
For VIN = VIH (min)
40
1
K
M
5
VHYS
Input Hysteresis
0.05 VDD
V
4
Notes
1.
SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2.
SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3.
VIN or VOUT = VSS to VDD. Does not apply to WP pin.
4.
This parameter is characterized but not tested.
5.
The input pull-down circuit is strong (40K) when the input voltage is below VIL and much weaker (1M)
when the input voltage is above VIH.


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