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AD14060L データシート(PDF) 2 Page - Analog Devices

部品番号 AD14060L
部品情報  Quad-SHARC DSP Multiprocessor Family
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ホームページ  http://www.analog.com
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AD14060L データシート(HTML) 2 Page - Analog Devices

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AD14060/AD14060L
–2–
REV. A
DETAILED DESCRIPTION
Architectural Features
ADSP-21060 Core
The AD14060/AD14060L is based on the powerful ADSP-21060
(SHARC) DSP chip. The ADSP-21060 SHARC combines a
high performance floating-point DSP core with integrated, on-
chip system features including a 4 Mbit SRAM memory, host
processor interface, DMA controller, serial ports, and both link
port and parallel bus connectivity for glueless DSP multiprocess-
ing, (see Figure 1). It is fabricated in a high speed, low power
CMOS process, and has a 25 ns instruction cycle time. The arith-
metic/ logic unit (ALU), multiplier and shifter all perform single-
cycle instructions, and the three units are arranged in parallel,
maximizing computational throughput.
The SHARC features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the pro-
gram memory (PM) bus transfers both instructions and data.
There is also an on-chip instruction cache which selectively
caches only those instructions whose fetches conflict with the
PM bus data accesses. This combines with the separate program
and data memory buses to enable three-bus operation for fetch-
ing an instruction and two operands, all in a single cycle. The
SHARC also contains a general purpose data register file, which
is a 10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For ex-
ample, the ADSP-21060 can conditionally execute a multiply, an
add, a subtract, and a branch, all in a single instruction.
The SHARCs contain 4 Mbits of on-chip SRAM each, orga-
nized as two blocks of 2 Mbits, which can be configured for
different combinations of code and data storage. The memory
can be configured as a maximum of 128K words of 32-bit data,
256K words of 16-bit data, 80K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to
4 megabits. A 16-bit floating-point storage format is supported
which effectively doubles the amount of data that may be stored
on chip. Conversion between the 32-bit floating point and 16-
bit floating point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA con-
troller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
Shared Memory Multiprocessing
The AD14060/AD14060L takes advantage of the powerful
multiprocessing features built into the SHARC. The SHARCs are
connected to maximize the performance of this cluster-of-four
architecture, and still allow for off-module expansion. The
AD14060/AD14060L in itself is a complete shared memory
multiprocessing system, as shown in Figure 3. The unified ad-
dress space of the SHARCs allows direct interprocessor ac-
cesses of each SHARCs’ internal memory. In other words, each
SHARC can directly access the internal memory and IOP registers
of each of the other SHARCs by simply reading or writing to the
appropriate address in multiprocessor memory space (see Figure
2)—this is called a direct read or direct write.
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
6
36
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, AND
DATA BUFFERS
I/O PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
ADDR
DATA
DATA
DATA
ADDR
ADDR
DATA
ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
JTAG
TEST AND
EMULATION
7
HOST PORT
ADDR BUS
MUX
IOA
17
IOD
48
MULTIPROCESSOR
INTERFACE
DUAL-PORTED SRAM
EXTERNAL
PORT
DATA BUS
MUX
48
32
24
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DATA
REGISTER
FILE
16 x 40-BIT
BARREL
SHIFTER
ALU
MULTIPLIER
DAG1
8 x 4 x 32
32
48
40/32
CORE PROCESSOR
DMA
CONTROLLER
PROGRAM
SEQUENCER
DAG2
8 x 4 x 24
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14060)


同様の部品番号 - AD14060L

メーカー部品番号データシート部品情報
logo
Analog Devices
AD14060L AD-AD14060L Datasheet
1Mb / 48P
   DSP Multiprocessor Family
REV. B
AD14060L AD-AD14060L_15 Datasheet
1Mb / 48P
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同様の説明 - AD14060L

メーカー部品番号データシート部品情報
logo
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