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AD1833 データシート(PDF) 11 Page - Analog Devices |
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AD1833 データシート(HTML) 11 Page - Analog Devices |
11 / 20 page REV. 0 AD1833 –11– MCLK Select The AD1833 allows the matching of available external MCLK frequencies to the required sample rate. The oversampling rate can be selected from 256 × f S, 512 × f S or 768 × f S by writing to Bit 4 and Bit 3. Internally the AD1833 requires an MCLK of 512 × fS; therefore, in the case of 256 × fS mode, a clock doubler is used, whereas in 768 × f S mode, a divide-by-3 block (/3) is first implemented, followed by a clock doubler. See Table XII. Table XII. MCLK Settings Bit 4 Bit 3 Oversample Ratio 0 0 256 × fS (MCLK × 2 Internally) 0 1 512 × fS 1 0 768 × f S (MCLK × 2/3 Internally) 1 1 Reserved Channel Zero Status The AD1833 provides individual logic output status indicators when zero data is sent to a channel for 1024 or more consecutive sample periods. There is also a global zero flag that indicates all channels contain zero data. The polarity of the active zero signal Table XIV. MCLK vs. Sample Rate Selection MCLK (MHz) Sampling Rate fS (kHz) Interpolator Mode 256 fS 512 fS 768 fS 32 8 × (Normal) 64 4 × (Double) 8.192 16.384 24.576 128 2 × (4 Times) 44.1 8 × (Normal) 88.2 4 × (Double) 11.2896 22.5792 33.8688 176.4 2 × (4 Times) 48 8 × (Normal) 96 4 × (Double) 12.288 24.576 36.864 192 2 × (4 Times) Table XV. Volume Control Registers Address Reserved * Volume Control 15–12 11 10 9–0 0 0 1 0 0 0 Channel 1 Volume Control (OUTL1) 0 0 1 1 Channel 2 Volume Control (OUTR1) 0 1 0 0 Channel 3 Volume Control (OUTL2) 0 1 0 1 Channel 4 Volume Control (OUTR2) 0 1 1 0 Channel 5 Volume Control (OUTL3) 0 1 1 1 Channel 6 Volume Control (OUTR3) *Must be programmed to zero. is programmable by writing to Control Bit 2, see Table XIII. The six individual channel flags are best used as three stereo zero flags by combining pairs of them through suitable logic gates. Then, when both the left and right input are zero for 1024 clock cycles, i.e., a stereo zero input for 1024 sample periods, the combined result of the two individual flags will go active indicating a stereo zero. Table XIII. Zero Detect Bit 2 Channel Zero Status 0 Active High 1 Active Low DAC Volume Control Registers The AD1833 has six volume control registers, one each for the six DAC channels. Volume control is exercised by writing to the relevant register associated with each DAC. This setting is used to attenuate the DAC output. Full-scale setting (all 1s) is equiva- lent to zero attenuation. See Table XV. |
同様の部品番号 - AD1833 |
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同様の説明 - AD1833 |
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