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AD5144BRUZ100-RL7 データシート(PDF) 11 Page - Analog Devices |
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AD5144BRUZ100-RL7 データシート(HTML) 11 Page - Analog Devices |
11 / 36 page Data Sheet AD5124/AD5144/AD5144A Rev. A | Page 11 of 36 Parameter1 Test Conditions/Comments Min Typ Max Unit Description t12 Standard mode 300 ns Fall time of SCL signal, tFCL Fast mode 20 + 0.1 CL 300 ns tSP3 Fast mode 0 50 ns Pulse width of suppressed spike 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode. Table 6. Control Pins Parameter Min Typ Max Unit Description t1 1 μs End command to LRDAC falling edge t2 50 ns Minimum LRDAC low time t3 0.1 10 μs RESET low time tEEPROM_PROGRAM 1 15 50 ms Memory program time (not shown in Figure 8) tEEPROM_READBACK 7 30 μs Memory readback time (not shown in Figure 8) tPOWER_UP2 75 μs Start-up time (not shown in Figure 8) tRESET 30 μs Reset EEPROM restore time (not shown in Figure 8) 1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. 2 Maximum time after VDD − VSS is equal to 2.3 V. SHIFT REGISTER AND TIMING DIAGRAMS DATA BITS DB8 DB15 (MSB) DB0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 ADDRESS BITS A0 A1 A2 C2 C1 C0 A3 C3 CONTROL BITS DB7 Figure 4. Input Shift Register Contents t7 t6 t2 t4 t11 t12 t6 t5 t10 t1 SCL SDA PS S P t3 t8 t9 Figure 5. I2C Serial Interface Timing Diagram (Typical Write Sequence) |
同様の部品番号 - AD5144BRUZ100-RL7 |
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同様の説明 - AD5144BRUZ100-RL7 |
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