データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD1958YRS データシート(PDF) 6 Page - Analog Devices

部品番号 AD1958YRS
部品情報  PLL/Multibit DAC
Download  8 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD1958YRS データシート(HTML) 6 Page - Analog Devices

  AD1958YRS Datasheet HTML 1Page - Analog Devices AD1958YRS Datasheet HTML 2Page - Analog Devices AD1958YRS Datasheet HTML 3Page - Analog Devices AD1958YRS Datasheet HTML 4Page - Analog Devices AD1958YRS Datasheet HTML 5Page - Analog Devices AD1958YRS Datasheet HTML 6Page - Analog Devices AD1958YRS Datasheet HTML 7Page - Analog Devices AD1958YRS Datasheet HTML 8Page - Analog Devices  
Zoom Inzoom in Zoom Outzoom out
 6 / 8 page
background image
REV. 0
AD1958
–6–
Table I. DAC Control Register
Bit 11:10
Bit 9:8
Bit 7
Bit 6
Bit 5:4
Bit 3:2
Bit 1:0
Interpolation
Serial Data
Serial Data
De-Emphasis
SPI Register
Factor
Width
Output Phase
Soft Mute
Format
Filter
Address
00 = 8
×*
00 = 24 Bits
*
0 = Noninverted
*
0 = No Mute
*
00 = I
2S*
00 = None
*
01
01 = 4
×
01 = 20 Bits
1 = Inverted
1 = Muted
00 = Right Justified
01 = 44.1 kHz
10 = 2
×
10 = 16 Bits
10 = DSP
10 = 32 kHz
11 = Not Allowed
11 = 16 Bits
11 = Left Justified
11 = 48 kH
z
*Default Setting
Table III. PLL Control Register
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7:6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1:0
PLL2
PLL1
XTAL
SPI
Power-
Power-
Power-
Clock
SCLK1
Frequency
SCLK2
MCLK
Register
Down
Down
Down
Configuration
fS
Select
Double
2
Select
Mode
Address
0 = On
1
0 = On
1
0 = On
1
0 = Mode 0
1
SCLK1 =
Reserved
Reserved
0 = Output
1
11
1 = PD
1 = PD
1 = PD
000: 36.864 MHz
1
Set to 0
Set to 0
1 = Input
100: 24.576 MHz
110: 33.8688 MHz
111: 22.5792 MHz
Other combinations reserved
SCLK2 = 16.9344 MHz
1 = Mode 1
00 = 48 kHz
0 = 256 fS
0 = Normal
0 = 22.5792 MHz
01 = Not
1 = 384 fS
1 =
1 = 512
fS
2
Allowed
fNOMINAL
2
10 = 32 kHz
11 = 44.1 kHz
NOTES
1Default Setting
2In Mode 1, Frequency Double affects SCLK1 always and SCLK2 in 512
fS mode.
PLL CLOCK SYSTEM
The PLL clock system is expected to be run from a 27 MHz
master clock supplied by the on-board crystal oscillator or an
external source connected to XIN. With the MCLK mode set
to Output, the 27 MHz clock is buffered out to the MCLK
pin. When set to Input, this pin is the 256 fS master clock input
for the DAC. SCLK0 is always set to 33.8688 MHz. SCLK1 is
intended to be used as a master audio clock and will be a multiple
of the sample rate set in the PLL control register (see Table III).
In Mode 0 (Bit 8), it can be set to 512 or 768 times either
44.1 kHz or 48 kHz. SCLK2 will be 16.3944 MHz (384
44.1 kHz). In Mode 1, SCLK1 can be set to 256, 384, 512,
or 768 times 32 kHz, 44.1 kHz, or 48 kHz. SCLK2 can be
set to a constant 22.5792 MHz (512
44.1 kHz) or 512 fS.
There are two loop filter pins, LF0 and LF1. They should each
be bypassed to PVDD by a network consisting of a 33 nF capaci-
tor in series with a 750
Ω resistor, paralleled with a 1.8 nF capacitor.
The 27 MHz Master Clock oscillator should have a crystal cut for
an 18 pF load connected between XIN and XOUT, with 22 pF
capacitors connected from XIN and XOUT to PGND.
Table II. DAC Volume Registers
Bit 15:2
Bit 1:0
Volume
SPI Register Address
14 Bits, Unsigned
00 = Left Volume
14 Bits, Unsigned
10 = Right Volume
Default is full volume
RESET/POWER-DOWN
RESET will set the control registers to their default settings. The
chip should be reset on power-up. After reset is deasserted, the
part will come out of reset on the next rising LRCLK.
SERIAL CONTROL PORT
The AD1958 has an SPI-compatible control port to permit
programming the internal control registers for the PLL and DAC.
The DAC output levels may be independently programmed
by means of an internal digital attenuator adjustable in 16384
linear steps.


同様の部品番号 - AD1958YRS

メーカー部品番号データシート部品情報
logo
Analog Devices
AD1958 AD-AD1958_15 Datasheet
634Kb / 8P
   PLL/Multibit DAC
REV. 0
More results

同様の説明 - AD1958YRS

メーカー部品番号データシート部品情報
logo
Analog Devices
AD1959 AD-AD1959 Datasheet
107Kb / 8P
   PLL/Multibit DAC
REV. 0
AD1958 AD-AD1958_15 Datasheet
634Kb / 8P
   PLL/Multibit DAC
REV. 0
AD1959 AD-AD1959_15 Datasheet
104Kb / 8P
   PLL/Multibit DAC
REV. 0
AD1855 AD-AD1855 Datasheet
233Kb / 15P
   Stereo, 96 kHz, Multibit DAC
REV. B
AD1854 AD-AD1854_15 Datasheet
396Kb / 12P
   Stereo, 96 kHz, Multibit DAC
REV. A
AD1854 AD-AD1854 Datasheet
390Kb / 12P
   Stereo, 96 kHz, Multibit DAC
REV. A
AD1855 AD-AD1855_15 Datasheet
234Kb / 15P
   Stereo, 96 kHz, Multibit DAC
REV. B
AD1853JRSZ AD-AD1853JRSZ Datasheet
358Kb / 16P
   Stereo, 24-Bit, 192 kHz, Multibit  DAC
REV. A
AD1853 AD-AD1853 Datasheet
416Kb / 16P
   Stereo, 24-Bit, 192 kHz, Multibit DAC
REV. A
AD1853 AD-AD1853_15 Datasheet
358Kb / 16P
   Stereo, 24-Bit, 192 kHz, Multibit DAC
REV. A
More results


Html Pages

1 2 3 4 5 6 7 8


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com