データシートサーチシステム |
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AD5011B データシート(PDF) 5 Page - Analog Devices |
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AD5011B データシート(HTML) 5 Page - Analog Devices |
5 / 8 page AD5011 –5– REV PrA PRELIMINARY TECHNICAL DATA D1 1 D1 0 D 1 D0 ADCCL K t 6 t 10 D1 1 D 1 0 D9 SCL K SDO t 7 t 8 t 9 D1 1 D1 0 D 1 D0 D1 3 D1 2 D 1 D 0 TxC LK t 14 t 11 T xSYNC t 13 X t 12 X D1 1 D2 D1 3 D 1 2 TxD AT A t 15 Figure 2. ADC Timing (1160 kHz < ADCCLK <= 2320 kHz) Figure 3. DAC Timing Figure 4. Control Interface R/W SEL2 D1 0 D1 DO SEL1 D1 1 SEL0 SPICL K t 17 t 18 TFS t 20 t 19 DT t 16 t 21 D1 0 D1 DO D1 1 DR (R/W = 1) DR (R/W = 0 t 22 t 23 SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges The rising edge of TxSYNC can occur anywhere as long at the TxSYNC low time exceeds one TxCLK period. The TxSYNC falling edge must occur after the TxCLK rising edge which captures the LSB of the previous word. This ensures correct loading into the DAC. The first 14 bits are loaded into the DAC, the 2 LSBs being don't cares. If R/ W = 1, the selected register's contents will be output on DR. If R/W = 0, no data will be output on DR. The SEL bits identify which of the four register banks is being written to. The 12 LSBs contain the word. When the AD5011 is reset using RESETB, the registers are reset to zero. |
同様の部品番号 - AD5011B |
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同様の説明 - AD5011B |
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