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AD5516-1 データシート(PDF) 10 Page - Analog Devices |
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AD5516-1 データシート(HTML) 10 Page - Analog Devices |
10 / 16 page REV. 0 AD5516 –10– Table I illustrates ideal analog output versus DAC code. Table I. DAC Register Contents AD5516-1 MSB LSB Analog Output, VOUT 1111 1111 1111 VREF_IN × 2.5/3 – 1 LSB 1000 0000 0000 0 V 0000 0000 0000 –VREF_IN × 2.5/3 MODES OF OPERATION The AD5516 has two modes of operation. Mode 1 (MODE bits = 00): The user programs a 12-bit data word to one of 16 channels via the serial interface. This word is loaded into the addressed DAC register and is then converted into an analog output voltage. During conversion the BUSY output is low and all SCLK pulses are ignored. At the end of a conversion BUSY goes high indicating that the update of the addressed DAC is complete. It is recommended that SCLK is not pulsed while BUSY is low. Mode 1 conversion takes 25 µs typ. Mode 2 (MODE bits = 01 or 10): Mode 2 operation allows the user to increment or decrement the DAC output in 0.25 LSB steps, resulting in a 14-bit monotonic DAC. The amount by which the DAC output is incremented or decremented is determined by Mode 2 bits DB6–DB0, e.g., for a 0.25 LSB increment/decrement DB6...DB0 = 0000001, while for a 2.5 LSB increment/decrement, DB6...DB0 = 0001010. The MODE bits determine whether the DAC data is incremented (01) or decremented (10). The maximum amount that the user is allowed to increment or decrement the DAC output is 127 steps of 0.25 LSB, i.e., DB6...DB0 = 1111111. Mode 2 update takes approximately 1 µs. The Mode 2 feature allows increased resolution but overall increment/decrement accu- racy varies with increment/decrement step as shown in TPC 14. Mode 2 is useful in applications where greater resolution is required, for example, in servo applications requiring fine-tune to 14-bit resolution. FUNCTIONAL DESCRIPTION The AD5516 consists of sixteen 12-bit DACs in a single package. A single reference input pin (REF_IN) is used to provide a 3 V reference for all 16 DACs. To update a DAC’s output voltage the required DAC is addressed via the 3-wire serial interface. Once the serial write is complete, the selected DAC converts the code into an output voltage. The output amplifiers translate the DAC output range to give the appropriate voltage range ( ±2.5 V, ±5 V, or ±10 V) at output pins VOUT0 to VOUT15. The AD5516 uses a self-calibrating architecture to achieve 12-bit performance. The calibration routine servos to select the appropriate voltage level on an internal 14-bit resolution DAC. Noise during the calibration ( BUSY low period) can result in the selection of a voltage within a ±0.25 LSB band around the normal selected voltage. See TPC 10. It is essential to minimize noise on REFIN for optimal perfor- mance. The AD780’s specified decoupling makes it the ideal reference to drive the AD5516. On power-on, all DACs power up to a reset value (see RESET section). DIGITAL-TO-ANALOG SECTION The architecture of each DAC channel consists of a resistor- string DAC followed by an output buffer amplifier. The voltage at the REF_IN Pin provides the reference voltage for the corre- sponding DAC. The input coding to the DAC is offset binary; this results in ideal DAC output voltages as follows: AD5516-1 V VD V DAC REF IN N REF IN = ×× × × × 22 5 32 25 3 __ . – . AD5516-2 V VD V DAC REF IN N REF IN = ×× × × × 42 5 32 22 5 3 __ . – . AD5516-3 V VD V DAC REF IN N REF IN = ×× × × × 82 5 32 42 5 3 __ . – . Where: D = decimal equivalent of the binary code that is loaded to the DAC register, i.e., 0–4096 N = DAC resolution = 12 0 0 A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB LSB MODE BITS ADDRESS BITS DATA BITS Figure 4. Mode 1 Data Format 0 1 A3 A2 A1 A0 0 0 0 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB LSB MODE BITS ADDRESS BITS 7 INCREMENT BITS 1 0 A3 A2 A1 A0 0 0 0 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB LSB MODE BITS ADDRESS BITS 7 DECREMENT BITS Figure 5. Mode 2 Data Format |
同様の部品番号 - AD5516-1 |
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同様の説明 - AD5516-1 |
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