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AD5541LR データシート(PDF) 3 Page - Analog Devices

部品番号 AD5541LR
部品情報  5 V, Serial-Input Voltage-Output, 16-Bit DACs
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD5541LR データシート(HTML) 3 Page - Analog Devices

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AD5541/AD5542
–3–
REV. A
SCLK
CS
DIN
DB15
LDAC*
DB0
t1
*AD5542 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
t2
t3
t5
t6
t7
t8
t9
t11
t4
t10
t12
Figure 1. Timing Diagram
TIMING CHARACTERISTICS1, 2
Limit at TMIN, TMAX
Parameter
All Versions
Unit
Description
fSCLK
25
MHz max
SCLK Cycle Frequency
t1
40
ns min
SCLK Cycle Time
t2
20
ns min
SCLK High Time
t3
20
ns min
SCLK Low Time
t4
15
ns min
CS Low to SCLK High Setup
t5
15
ns min
CS High to SCLK High Setup
t6
35
ns min
SCLK High to CS Low Hold Time
t7
20
ns min
SCLK High to CS High Hold Time
t8
15
ns min
Data Setup Time
t9
0
ns min
Data Hold Time
t10
30
ns min
LDAC Pulsewidth
t11
30
ns min
CS High to LDAC Low Setup
t12
30
ns min
CS High Time Between Active Periods
NOTES
1Guaranteed by design. Not production tested.
2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
(VDD = 5 V
5%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless
otherwise noted.)


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