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データシートサーチシステム |
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データシートサーチシステム |
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AD5305BRM-REEL データシート(PDF) 4 Page - Analog Devices |
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AD5305BRM-REEL データシート(HTML) 4 Page - Analog Devices |
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4 / 20 page  REV. F –4– AD5305/AD5315/AD5325 TIMING CHARACTERISTICS1, 2 (V DD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX Parameter (A, B Version) Unit Conditions/Comments fSCL 400 kHz max SCL Clock Frequency t1 2.5 µs min SCL Cycle Time t2 0.6 µs min tHIGH, SCL High Time t3 1.3 µs min tLOW, SCL Low Time t4 0.6 µs min tHD,STA, Start/Repeated Start Condition Hold Time t5 100 ns min tSU,DAT, Data Setup Time t6 3 0.9 µs max tHD,DAT, Data Hold Time 0 µs min tHD,DAT, Data Hold Time t7 0.6 µs min tSU,STA, Setup Time for Repeated Start t8 0.6 µs min tSU,STO, Stop Condition Setup Time t9 1.3 µs min tBUF, Bus Free Time between a STOP and a START Condition t10 300 ns max tR, Rise Time of SCL and SDA when Receiving 0 ns min tR, Rise Time of SCL and SDA when Receiving (CMOS Compatible) t11 250 ns max tF, Fall Time of SDA when Transmitting 0 ns min tF, Fall Time of SDA when Receiving (CMOS Compatible) 300 ns max tF, Fall Time of SCL and SDA when Receiving 20 + 0.1CB 4 ns min tF, Fall Time of SCL and SDA when Transmitting CB 400 pF max Capacitive Load for Each Bus Line NOTES 1See Figure 1. 2Guaranteed by design and characterization; not production tested. 3A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V IH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4C B is the total capacitance of one bus line in pF. t R and tF measured between 0.3 VDD and 0.7 VDD. Specifications subject to change without notice. SCL SDA START CONDITION t9 t3 t4 t6 t2 t5 t7 t8 t1 t4 t11 t10 REPEATED START CONDITION STOP CONDITION Figure 1. 2-Wire Serial Interface Timing Diagram |
同様の部品番号 - AD5305BRM-REEL |
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同様の説明 - AD5305BRM-REEL |
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