データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD802-155KR データシート(PDF) 1 Page - Analog Devices

部品番号 AD802-155KR
部品情報  Clock Recovery and Data Retiming Phase-Locked Loop
Download  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD802-155KR データシート(HTML) 1 Page - Analog Devices

  AD802-155KR Datasheet HTML 1Page - Analog Devices AD802-155KR Datasheet HTML 2Page - Analog Devices AD802-155KR Datasheet HTML 3Page - Analog Devices AD802-155KR Datasheet HTML 4Page - Analog Devices AD802-155KR Datasheet HTML 5Page - Analog Devices AD802-155KR Datasheet HTML 6Page - Analog Devices AD802-155KR Datasheet HTML 7Page - Analog Devices AD802-155KR Datasheet HTML 8Page - Analog Devices AD802-155KR Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 12 page
background image
FUNCTIONAL BLOCK DIAGRAM
VCO
DATA
INPUT
AD800/AD802
CD
RETIMED
DATA
OUTPUT
FRAC
OUTPUT
LOOP
FILTER
ØDET
fDET
COMPENSATING
ZERO
RECOVERED
CLOCK
OUTPUT
RETIMING
DEVICE
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Clock Recovery and Data Retiming
Phase-Locked Loop
AD800/AD802*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
PRODUCT DESCRIPTION
The AD800 and AD802 employ a second order phase-locked
loop architecture to perform clock recovery and data retiming
on Non-Return to Zero, NRZ, data. This architecture is
capable of supporting data rates between 20 Mbps and 160
Mbps. The products described here have been defined to work
with standard telecommunications bit rates. 45 Mbps DS-3 and
52 Mbps STS-1 are supported by the AD800-45 and
AD800-52 respectively. 155 Mbps STS-3 or STM-1 are
supported by the AD802-155.
Unlike other PLL-based clock recovery circuits, these devices
do not require a preamble or an external VCXO to lock onto
input data. The circuit acquires frequency and phase lock using
two control loops. The frequency acquisition control loop
initially acquires the clock frequency of the input data. The
phase-lock loop then acquires the phase of the input data, and
ensures that the phase of the output signals track changes in the
phase of the input data. The loop damping of the circuit is
dependent on the value of a user selected capacitor; this defines
jitter peaking performance and impacts acquisition time. The
devices exhibit 0.08 dB jitter peaking, and acquire lock on
random or scrambled data within 4
× 105 bit periods when
using a damping factor of 5.
FEATURES
Standard Products
44.736 Mbps—DS-3
51.84 Mbps—STS-1
155.52 Mbps—STS-3 or STM-1
Accepts NRZ Data, No Preamble Required
Recovered Clock and Retimed Data Outputs
Phase-Locked Loop Type Clock Recovery—No Crystal
Required
Random Jitter: 20 Peak-to-Peak
Pattern Jitter: Virtually Eliminated
10KH ECL Compatible
Single Supply Operation: –5.2 V or +5 V
Wide Operating Temperature Range: –40 C to +85 C
During the process of acquisition the frequency detector
provides a Frequency Acquisition (FRAC) signal which
indicates that the device has not yet locked onto the input data.
This signal is a series of pulses which occur at the points of cycle
slip between the input data and the synthesized clock signal.
Once the circuit has acquired frequency lock no pulses occur at
the FRAC output.
The inclusion of a precisely trimmed VCO in the device
eliminates the need for external components for setting center
frequency, and the need for trimming of those components. The
VCO provides a clock output within
±20% of the device center
frequency in the absence of input data.
The AD800 and AD802 exhibit virtually no pattern jitter, due
to the performance of the patented phase detector. Total loop
jitter is 20
° peak-to-peak. Jitter bandwidth is dictated by mask
programmable fractional loop bandwidth. The AD800, used for
data rates < 90 Mbps, has been designed with a nominal loop
bandwidth of 0.1% of the center frequency. The AD802, used
for data rates in excess of 90 Mbps, has a loop bandwidth of
0.08% of center frequency.
All of the devices operate with a single +5 V or –5.2 V supply.
*Protected by U.S. Patent No. 5,027,085.


同様の部品番号 - AD802-155KR

メーカー部品番号データシート部品情報
logo
Analog Devices
AD8021 AD-AD8021 Datasheet
467Kb / 20P
   Low Noise, High Speed Amplifier for 16-Bit Systems
REV. D
AD8021 AD-AD8021 Datasheet
490Kb / 24P
   Low Power, 1 nV/?숰z, G ??10 Stable, Rail-to-Rail Output Amplifier
REV. 0
AD8021 AD-AD8021 Datasheet
860Kb / 32P
   Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface
REV. 0
AD8021 AD-AD8021 Datasheet
405Kb / 20P
   Dual-Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with 4-Quadrant Resistors
REV. D
AD8021 AD-AD8021 Datasheet
868Kb / 32P
   14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC
REV. 0
More results

同様の説明 - AD802-155KR

メーカー部品番号データシート部品情報
logo
Analog Devices
AD800 AD-AD800_15 Datasheet
141Kb / 12P
   Clock Recovery and Data Retiming Phase-Locked Loop
REV. B
AD802 AD-AD802_15 Datasheet
141Kb / 12P
   Clock Recovery and Data Retiming Phase-Locked Loop
REV. B
AD805 AD-AD805_15 Datasheet
324Kb / 12P
   Data Retiming Phase-Locked Loop
REV. 0
AD805 AD-AD805 Datasheet
318Kb / 12P
   DATA RETIMING PHASE LOCKED LOOP
REV. 0
logo
Pericom Semiconductor C...
PI6C2502 PERICOM-PI6C2502 Datasheet
371Kb / 6P
   Phase-Locked Loop Clock Driver
logo
Arizona Microtek, Inc
AZ12000 AZM-AZ12000 Datasheet
188Kb / 13P
   Phase-Locked Loop Clock Generator
logo
Pericom Semiconductor C...
PI6C2302 PERICOM-PI6C2302 Datasheet
279Kb / 4P
   Phase-Locked Loop Clock Driver
PI6C2501A PERICOM-PI6C2501A Datasheet
50Kb / 4P
   Phase-Locked Loop Clock Driver
PI6C2502A PERICOM-PI6C2502A Datasheet
276Kb / 4P
   Phase-Locked Loop Clock Driver
PI6C2501 PERICOM-PI6C2501 Datasheet
235Kb / 4P
   Phase-Locked Loop Clock Driver
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com