データシートサーチシステム |
|
AD8013AR-14 データシート(PDF) 11 Page - Analog Devices |
|
AD8013AR-14 データシート(HTML) 11 Page - Analog Devices |
11 / 12 page –11– REV. A AD8013 FREQUENCY – Hz 1.5 1.0 –2.0 1M 1G 10M 100M 0.5 0 –0.5 –1.0 –1.5 G = +2 RL = 150Ω VS = +5V VS = ±5V Figure 34. Closed-Loop Gain Matching vs. Frequency FREQUENCY – Hz 10 8 2 4 6 –1.0 0.5 0 –0.5 1.0 100k 100M 1M 10M VS = +5V VS = ±5V G = +2 RL = 150Ω G = +2 RL = 150Ω DELAY MATCHING DELAY VS = +5V VS = ±5V Figure 35. Group Delay and Group Delay Matching vs. Frequency, G = +2, RL = 150 Ω Disable Mode Operation Pulling the voltage on any one of the Disable pins about 1.6 V up from the negative supply will put the corresponding amplifier into a disabled, powered down, state. In this condition, the amplifier’s quiescent current drops to about 0.3 mA, its output becomes a high impedance, and there is a high level of isolation from input to output. In the case of the gain of two line driver for example, the impedance at the output node will be about the same as for a 1.6 k Ω resistor (the feedback plus gain resistors) in parallel with a 12 pF capacitor and the input to output isolation will be about 66 dB at 5 MHz. Leaving the Disable pin disconnected (floating) will leave the corresponding amplifier operational, in the enabled state. The input impedance of the disable pin is about 40 k Ω in parallel with a few picofarads. When driven to 0 V, with the negative supply at –5 V, about 100 µA flows into the disable pin. When the disable pins are driven by complementary output CMOS logic, on a single 5 V supply, the disable and enable times are about 50 ns. When operated on dual supplies, level shifting will be required from standard logic outputs to the Disable pins. Figure 36 shows one possible method which results in a negligible increase in switching time. +5V 10k TO DISABLE PIN VI VI HIGH => AMPLIFIER ENABLED VI LOW => AMPLIFIER DISABLED –5V 4k 8k Figure 36. Level Shifting to Drive Disable Pins on Dual Supplies The AD8013’s input stages include protection from the large differential input voltages that may be applied when disabled. Internal clamps limit this voltage to about ±3 V. The high input to output isolation will be maintained for voltages below this limit. 3:1 Video Multiplexer Wiring the amplifier outputs together will form a 3:1 mux with excellent switching behavior. Figure 37 shows a recommended configuration which results in –0.1 dB bandwidth of 35 MHz and OFF channel isolation of 60 dB at 10 MHz on ±5 V supplies. The time to switch between channels is about 50 ns. Switching time is virtually unaffected by signal level. 665 Ω 75 Ω VIN1 84 Ω 845 Ω DISABLE 1 VOUT 75 Ω 75 Ω CABLE –VS 7 6 5 4 +VS 1 665 Ω 75 Ω VIN2 84 Ω 845 Ω DISABLE 2 14 13 12 2 665 Ω 75 Ω VIN3 84 Ω 845 Ω 8 9 10 3 11 DISABLE 3 Figure 37. A Fast Switching 3:1 Video Mux (Supply Bypassing Not Shown) 10 0% 100 90 200ns 500mV 5V Figure 38. Channel Switching Characteristic for the 3:1 Mux |
同様の部品番号 - AD8013AR-14 |
|
同様の説明 - AD8013AR-14 |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |