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LM10011 データシート(PDF) 3 Page - Texas Instruments

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部品番号 LM10011
部品情報  6/4-Bit VID Programmable Current DAC for Point of Load Regulators with Adjustable Start-Up Current
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

LM10011 データシート(HTML) 3 Page - Texas Instruments

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LM10011
www.ti.com
SNVS822 – DECEMBER 2012
ABSOLUTE MAXIMUM RATINGS
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD, EN, IDAC_OUT, MODE
–0.3
6
V
VIDA, VIDB, VIDC, VIDS
–0.3
6
V
ESD Rating(3)
Human Body Model
2
kV
Storage Temperature
–65
+150
°C
Junction Temperature
+150
°C
(1)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
(2)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3)
The human body model is a 100 pF capacitor discharged through a 1.5k
Ω resistor into each pin.
OPERATING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
VDD
2.97
5.5
V
IDAC_OUT
-0.3
VDD-1.75
V
VIDA, VIDB, VIDC, VIDS, EN, MODE
-0.3
5.5
V
Junction Temperature
−40
+125
°C
Ambient Temperature
−40
+125
°C
THERMAL INFORMATION
LM10011
THERMAL METRIC(1)
SON-10
UNITS
10 PINS
θJA
Junction-to-ambient thermal resistance(2)
52.1
θJCtop
Junction-to-case (top) thermal resistance(3)
30.6
θJB
Junction-to-board thermal resistance(4)
26.8
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.9
ψJB
Junction-to-board characterization parameter(6)
26.9
θJCbot
Junction-to-case (bottom) thermal resistance(7)
7.7
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Copyright © 2012, Texas Instruments Incorporated
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