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3X38FTR データシート(PDF) 5 Page - Agere Systems |
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3X38FTR データシート(HTML) 5 Page - Agere Systems |
5 / 64 page Lucent Technologies Inc. 5 Preliminary Data Sheet 3X38FTR 208-Pin SQFP September 2000 OCTAL-FET for 10Base-T/100Base-TX/FX Description RMII Mode The reduced media independent interface (RMII) is a low pin count interface specification promulgated by the RMII consortium. This specification reduces the total number of pins from 16 for the IEEE 802.3U MII inter- face to seven for the RMII. Architecturally, the RMII specification provides for an additional reconciliation sublayer on either side of the MII but, in the 3X38, has been implemented in the absence of the MII. The management interface (MDIO/MDC) remains iden- tical to that defined in IEEE 802.3u. The RMII specification has the following characteris- tics: s It supports 10 Mbits/s and 100 Mbits/s data rates. s A single 50 MHz clock reference is sourced from MAC to PHY or from an external shared source. s It provides independent 2-bit wide transmit and receive data paths. SMII Mode The serial media independent interface (SMII) is a low pin count interface specification promulgated by Cisco*. This specification reduces the total number of pins from 16 for the IEEE 802.3u MII interface to two for the SMII. Architecturally, the SMII specification pro- vides for an additional reconciliation sublayer on either side of the MII but, in the 3X38, has been implemented in the absence of the MII. The management interface (MDIO/MDC) remains iden- tical to that defined in IEEE 802.3u. The SMII specification has the following characteristics: s It supports 10 Mbits/s and 100 Mbits/s data rates. s A single 125 MHz clock reference is sourced from MAC to PHY or from an external shared source. s It provides independent serial transmit and receive data paths. LED Control LEDs can be accessed in one of the following modes: s Serial mode. In this mode, all of the LEDs are time- division multiplexed onto one pin, with a second pin acting as the clock and a third as a strobe. All LEDs and all channels share the same pins. s Parallel mode. In this mode, each LED and each channel has its own pin. There is a total of four LED pins per channel for a total of 32 pins. s Bicolor mode. In this mode, each channel has two outputs to control a bicolor LED. One LED can be used for each port, indicating link and activity. In all modes, the LEDs can be operated as follows: s LED stretch. s LED blink. s No stretch or blink. Clocking The 3X38 operates with a 50 MHz clock input when in the RMII mode, and with a 125 MHz clock input when in the SMII mode. FX Mode Each individual port of the 3X38 can be operated in 100Base-FX mode by selecting it through the pin pro- gram option (FX_MODE_EN[7:0]), or through the reg- ister bit (register 29, bit 0). When operating in FX mode, the twisted-pair I/O pins are reused as the fiber-optic transceiver I/O data pins, and the fiber-optic signal detect (FOSD) inputs are enabled. When a port is placed in FX mode, it will automatically configure the port for 100Base-FX operation (and the register bit control will be ignored) such that: s The far-end fault signaling option will be enabled. s The MLT-3 encoding/decoding will be disabled. s Scrambler/descrambler will be disabled. s Autonegotiation will be disabled. s The signal detect inputs will be activated. s 10Base-T will be disabled. * Cisco is a registered trademark of Cisco Systems. |
同様の部品番号 - 3X38FTR |
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同様の説明 - 3X38FTR |
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