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74ACTQ16374SSC データシート(PDF) 5 Page - Fairchild Semiconductor

部品番号 74ACTQ16374SSC
部品情報  16-Bit D-Type Flip-Flop with 3-STATE Outputs
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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Extended AC Electrical Characteristics
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (tOST).
Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 14: The Output Disable Time is dominated by the RC network (500
Ω, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
TA = −40°C to +85°C
CL = 50 pF
TA = −40°C to +85°C
Symbol
Parameter
16 Outputs Switching
CL = 250 pF
Units
(Note 10)
(Note 11)
Min
Typ
Max
Min
Max
tPLH
Propagation Delay
4.7
13.3
6.6
16.3
ns
tPHL
Data to Output
4.6
11.4
6.4
15.5
tPZH
Output Enable Time
3.5
10.4
(Note 13)
ns
tPZL
3.8
10.9
tPHZ
Output Disable Time
3.4
8.5
(Note 14)
ns
tPLZ
3.1
8.1
tOSHL
Pin to Pin Skew
1.3
ns
(Note 12)
HL Data to Output
tOSLH
Pin to Pin Skew
2.1
ns
(Note 12)
LH Data to Output
tOST
Pin to Pin Skew
4.0
ns
(Note 12)
LH/HL Data to Output
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0V
CPD
Power Dissipation Capacitance
30
pF
VCC = 5.0V


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