www.fairchildsemi.com

2

Unit Loading/Fan Out

Functional Description

The 74F175 consists of four edge-triggered D-type flip-

flops with individual D inputs and Q and Q outputs. The

Clock and Master Reset are common. The four flip-flops

will store the state of their individual D inputs on the

LOW-to-HIGH clock (CP) transition, causing individual Q

and Q outputs to follow. A LOW input on the Master Reset

(MR) will force all Q outputs LOW and Q outputs HIGH

independent of Clock or Data inputs. The 74F175 is useful

for general logic applications where a common Master

Reset and Clock are acceptable.

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

 = LOW-to-HIGH Clock Transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

Data Inputs

1.0/1.0

20

µA/−0.6 mA

CP

Clock Pulse Input (Active Rising Edge)

1.0/1.0

20

µA/−0.6 mA

MR

Master Reset Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

True Outputs

50/33.3

−1 mA/20 mA

Complement Outputs

50/33.3

−1 mA/20 mA

Inputs

Outputs

MR

CP

LX

X

L

H

H



HH

L

H



LL

H