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74FR573PC データシート(PDF) 2 Page - Fairchild Semiconductor |
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74FR573PC データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Functional Description The 74FR573 contains eight D-type latches with 3-STATE output buffers. When the latch enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode, but this does not interfere with entering new data into the latches. Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram Inputs Output OE LE Dn On LH H H LH L L LL X On − 1 H X X High Z State |
同様の部品番号 - 74FR573PC |
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同様の説明 - 74FR573PC |
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