74FR1074PC datasheet(6/8 Pages) FAIRCHILD

部品番号	74FR1074PC

部品情報	Dual D-Type Flip-Flop

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AC Electrical Characteristics 74FR1074

Note 5: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged

device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions

both HL and LH (tOST). tOST is guaranteed by design.

AC Operating Requirements 74FR1074

Note 6: This specification is guaranteed by design.

Symbol

Parameter

TA = +25°CTA = 0°C to +70°C

Units

VCC = +5.0V

CL = 50 pF

Min

Typ

Max

Min

Max

fMAX

Maximum Clock Frequency

120

160

120

MHz

tPLH

Propagation Delay

2.5

4.0

5.5

2.5

5.5

ns

tPHL

CPn to Qn or Qn

3.0

5.0

6.5

3.0

6.5

tPLH

Propagation Delay

1.5

3.5

5.5

1.5

5.5

ns

tPHL

CDn or SDn to Qn or Qn

2.0

5.5

7.0

2.0

7.0

tOSHL

Pin to Pin Skew

1.5

ns

(Note 5)

for HL Transitions

tOSLH

Pin to Pin Skew

1.5

ns

(Note 5)

for LH Transitions

tOST

Pin to Pin Skew

3.5

ns

(Note 5)

for HL/LH Transitions

tQ/Q

True/Complement

2.0

ns

(Note 5)

Output Skew

tPS

Pin (Signal)

2.0

ns

(Note 5)

Transition Variation

TA = +25°CTA = 0°C = +70°C

Symbol

Parameter

VCC = +5.0V

Units

CL = 50 pF

Min

Max

Min

Max

tS(H)

Setup Time, HIGH or LOW

2.0

ns

tS(L)

Dn to CPn

2.0

tH(H)

Hold Time, HIGH or LOW

0

ns

tH(L)

Dn to CPn

00

tW(H)

CPn Pulse Width

3.3

ns

tW(L)

HIGH or LOW

3.3

(Note 6)

tW(L)

SDn or CDn Pulse Width

4.0

ns

tREC

Recovery Time

2.0

ns

SDn or CDn to CPn

同様の部品番号 - 74FR1074PC

メーカー	部品番号	データシート	部品情報
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National Semiconductor ...	74FR16245Q	151Kb / 6P	16-Bit Transceiver with TRI-STATE Outputs
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