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74LCX821MSA データシート(PDF) 2 Page - Fairchild Semiconductor |
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74LCX821MSA データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Pin Descriptions Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impendance = LOW-to-HIGH Transition NC = No Change Functional Description The LCX821 consists of ten edge-triggered flip-flops with individual D-type inputs with 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The ten flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CLK) transition. With the Output Enable (OE) LOW, the contents of the ten flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description D0–D9 Data Inputs CLK Clock Input OE Output Enable Input O0–O9 3-STATE Latch Outputs Inputs Internal Outputs Function OE CLK D Q On H H L NC Z Hold H H H NC Z Hold H L L Z Load H H H Z Load L L L L Data Available L H H H Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data |
同様の部品番号 - 74LCX821MSA |
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同様の説明 - 74LCX821MSA |
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