データシートサーチシステム |
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74LVTH574SJ データシート(PDF) 2 Page - Fairchild Semiconductor |
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74LVTH574SJ データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Logic Symbols IEEE/IEC Connection Diagram Pin Descriptions Truth Table H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance LOW-to-HIGH Transition Oo Previous Oo before HIGH to LOW of CP Functional Description The LVT574 and LVTH574 consist of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the out- puts. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs Inputs Outputs Dn CP OE On H LH L LL XL L Oo XX H Z |
同様の部品番号 - 74LVTH574SJ |
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同様の説明 - 74LVTH574SJ |
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