データシートサーチシステム |
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74VCX162839MTD データシート(PDF) 2 Page - Fairchild Semiconductor |
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74VCX162839MTD データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 Connection Diagram Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Functional Description The 74VCX162839 consists of twenty selectable non- inverting buffers or registers with word wide controls. Mode functionality is selected through operation of the CP and REGE pin as shown by the truth table. When REGE is held at a logic “1” the device operates as a 20-bit register. Data is transferred from In to On on the rising edge of the CP pin. When the REGE pin is held at a logic “0” the device oper- ates in a flow through mode and data propagates directly from the In to the On outputs. All outputs can be 3-stated by holding the OE pin at a logic “1.” Logic Diagram Inputs Outputs CP REGE In OE On ↑ HH L H ↑ HL L L XL H L H X LLL L XXX H Z |
同様の部品番号 - 74VCX162839MTD |
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同様の説明 - 74VCX162839MTD |
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