October 1987

Revised January 1999

© 1999 Fairchild Semiconductor Corporation

DS005983.prf

www.fairchildsemi.com

CD4094BC

8-Bit Shift Register/Latch with 3-STATE Outputs

General Description

The CD4094BC consists of an 8-bit shift register and a 3-

STATE 8-bit latch. Data is shifted serially through the shift

register on the positive transition of the clock. The output of

output, Q

′

The output of each stage of the shift register feeds a latch,

which latches data on the negative edge of the STROBE

input. When STROBE is HIGH, data propagates through

the latch to 3-STATE output gates. These gates are

enabled when OUTPUT ENABLE is taken HIGH.

Features

s Wide supply voltage range:

3.0V to 18V

s Low power TTL compatibility:

Fan out of 2 driving 74L or 1 driving 74LS

s 3-STATE outputs

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP and SOIC

Top View

Truth Table

X

= Don't Care

 = HIGH-to-LOW

 = LOW-to-HIGH

Order Number

Package Number

Package Description

CD4094BCWM

M16B

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

CD4094BCN

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Clock

Output

Strobe

Data

Parallel Outputs

Serial Outputs

Enable

Q1

(Note 1)

Q



0

X

X

Hi-Z

Hi-Z

Q7

No Change



0

X

X

Hi-Z

Hi-Z

No Change

Q7



1

0

X

No Change No Change

Q7

No Change



11

0

0

Q7

No Change



11

1

1

Q7

No Change



1

1

1

No Change No Change No Change

Q7