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DM74ALS640AWM データシート(PDF) 1 Page - Fairchild Semiconductor |
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DM74ALS640AWM データシート(HTML) 1 Page - Fairchild Semiconductor |
1 / 4 page © 2000 Fairchild Semiconductor Corporation DS008640 www.fairchildsemi.com August 1985 Revised February 2000 DM74ALS640A Inverting Octal Bus Transceiver General Description This inverting octal bus transceiver is designed for asyn- chronous two-way communication between data busses. This device transmits data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G) can be used to disable the device so the busses are effectively isolated. Features s Advanced Oxide-isolated Ion-implanted Schottky TTL process s Switching performance is guaranteed over full tempera- ture and VCC supply range s Switching performance specified at 50 pF s PNP input design reduces input loading Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Diagram Function Table L = LOW Logic Level H = HIGH Logic Level X = Either LOW or HIGH Logic Level Order Number Package Number Package Description DM74ALS640AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS640AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Control Inputs Operation G DIR LL B Data to A Bus LH A Data to B Bus HX Isolation |
同様の部品番号 - DM74ALS640AWM |
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同様の説明 - DM74ALS640AWM |
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