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DM74AS651NT データシート(PDF) 2 Page - Fairchild Semiconductor |
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DM74AS651NT データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Connection Diagram Function Table H = HIGH Level L = LOW Level X = Irrelevant ↑ = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Note 2: If the select control is LOW, the clocks can occur simultaneously. If the select control is HIGH, the clocks must be staggered in order to load both registers. INPUTS DATA I/O (Note 1) OPERATION OR FUNCTION GAB GBA CAB CBA SAB SBA A1 B1 DM74AS651 DM74AS652 THRU THRU A8 B8 L H H or L H or L X X Input Input Isolation Isolation LH ↑↑ X X Store A and B Data Store A and B Data LL X X X L Output Input Real Time B Data to A Bus Real Time B Data to A Bus LL X H or L X H Stored B Data to A Bus Stored B Data to A Bus HH X X L X Input Output Real Time A Data to B Bus Real Time A Data to B Bus H H H or L X H X Stored A Data to B Bus Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus Stored A Data to B Bus & Stored B Data to A Bus & Stored B Data to A Bus XH ↑ H or L X X Input Unspecified (Note 1) Store A, Hold B Store A, Hold B HH ↑↑ X (Note 2) X Input Output Store A in both registers Store A in both registers LX H or L ↑ X X Unspecified (Note 1) Input Hold A, Store B Hold A, Store B LL ↑↑ XX (Note 2) Output Input Store B in both registers Store B in both registers |
同様の部品番号 - DM74AS651NT |
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同様の説明 - DM74AS651NT |
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