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DM74S299 データシート(PDF) 2 Page - Fairchild Semiconductor

部品番号 DM74S299
部品情報  3-STATE 8-Bit Universal Shift/Storage Register
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

DM74S299 データシート(HTML) 2 Page - Fairchild Semiconductor

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Function Table
a...h
= The level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip-flop outputs are isolated
from the input/output terminals.
H
= HIGH Level
L
= LOW Logic Level
X
= Either LOW or HIGH Logic Level
QA0...QH0 = The output logic level of QX before the indicated input conditions were established.
QAn...QHn = The output logic level before the active transition (↑) of the clock input.
Note 1: When one or both output controls are HIGH the eight input/output terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected
Logic Diagram
Inputs
Inputs/Outputs
Outputs
Mode
Function
Output
Clear
Select
Control
Clock
Serial
A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH QA′ QH′
S1
S0
G1
(Note 1)
G2
(Note 1)
SL SR
Clear
L
X
L
L
L
X
X
X
L
L
L
L
L
L
L
L
L
L
LL
X
L
L
X
X
X
L
L
L
L
LL
L
L
L
L
Hold
H
L
L
L
L
X
X
X
QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0
HX
X
L
L
L
X
X
QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0
Shift
Right
HL
H
L
L
XH
H
QAn QBn QCn QDn QEn
QFn
QGn
HQGn
HL
H
L
L
XL
L
QAn QBn QCn QDn QEn
QFn
QGn
LQGn
Shift
Left
HH
L
L
L
HX
QBn QCn QDn QEn QFn QGn QHn
HQBn H
HH
L
L
L
LX
QBn QCn QDn QEn QFn QGn QHn
LQBn L
Load
H
H
H
X
X
XX
a
b
c
d
e
f
g
h
a
h


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