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DM74S51N データシート(PDF) 1 Page - Fairchild Semiconductor |
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DM74S51N データシート(HTML) 1 Page - Fairchild Semiconductor |
1 / 3 page © 2000 Fairchild Semiconductor Corporation DS006454 www.fairchildsemi.com August 1986 Revised April 2000 DM74S51 Dual 2-Wide 2-Input AND-OR-INVERT Gate General Description This device contains two independent combinations of gates each of which performs the logic AND-OR-INVERT function. Ordering Code: Connection Diagram Function Table H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level Order Number Package Number Package Description DM74S51N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Y = AB + CD Inputs Output AB CD Y HH X X L XX H H L All other H combinations |
同様の部品番号 - DM74S51N |
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同様の説明 - DM74S51N |
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