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AD9888KSZ-100 データシート(PDF) 1 Page - Analog Devices |
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AD9888KSZ-100 データシート(HTML) 1 Page - Analog Devices |
1 / 36 page 100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface Data Sheet AD9888 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved. FEATURES 170 MSPS maximum conversion rate 500 MHz programmable analog bandwidth 0.5 V to 1.0 V analog input range Less than 450 ps p-p PLL clock jitter at 170 MSPS 3.3 V power supply Full sync processing Sync detect for hot plugging 2:1 analog input mux 4:2:2 output format mode Midscale clamping Power-down mode Low power: <1 W typical at 170 MSPS APPLICATIONS RGB graphics processing LCD monitors and projectors Plasma display panels Scan converters Microdisplays Digital TV FUNCTIONAL BLOCK DIAGRAM HSYNC0 VSYNC0 VSYNC1 SOGIN0 SOGIN1 COAST HSYNC1 SERIAL REGISTER AND POWER MANAGEMENT DATACK HSOUT VSOUT SOGOUT AD9888 SYNC PROCESSING AND CLOCK GENERATION CLAMP DRA[7:0] DRB[7:0] DGA[7:0] DGB[7:0] DBA[7:0] DBB[7:0] ADC CLAMP RAIN1 RAIN0 8 8 8 ADC CLAMP 8 8 8 ADC CLAMP 2:1 MUX SCL SDA A0 8 8 8 2 GAIN1 GAIN0 BAIN1 BAIN0 2:1 MUX 2:1 MUX REF BYPASS 2:1 MUX 2:1 MUX 2:1 MUX CKINV CKEXT FILT REF Figure 1. GENERAL DESCRIPTION The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz. For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V. The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications. A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully program- mable via a 2-wire serial port. Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package. |
同様の部品番号 - AD9888KSZ-100 |
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同様の説明 - AD9888KSZ-100 |
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