データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AD9888KSZ-100 データシート(PDF) 1 Page - Analog Devices

部品番号 AD9888KSZ-100
部品情報  100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface
Download  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9888KSZ-100 データシート(HTML) 1 Page - Analog Devices

  AD9888KSZ-100 Datasheet HTML 1Page - Analog Devices AD9888KSZ-100 Datasheet HTML 2Page - Analog Devices AD9888KSZ-100 Datasheet HTML 3Page - Analog Devices AD9888KSZ-100 Datasheet HTML 4Page - Analog Devices AD9888KSZ-100 Datasheet HTML 5Page - Analog Devices AD9888KSZ-100 Datasheet HTML 6Page - Analog Devices AD9888KSZ-100 Datasheet HTML 7Page - Analog Devices AD9888KSZ-100 Datasheet HTML 8Page - Analog Devices AD9888KSZ-100 Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 36 page
background image
100 MSPS/140 MSPS/170 MSPS
Analog Flat Panel Interface
Data Sheet
AD9888
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2001–2011 Analog Devices, Inc. All rights reserved.
FEATURES
170 MSPS maximum conversion rate
500 MHz programmable analog bandwidth
0.5 V to 1.0 V analog input range
Less than 450 ps p-p PLL clock jitter at 170 MSPS
3.3 V power supply
Full sync processing
Sync detect for hot plugging
2:1 analog input mux
4:2:2 output format mode
Midscale clamping
Power-down mode
Low power: <1 W typical at 170 MSPS
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TV
FUNCTIONAL BLOCK DIAGRAM
HSYNC0
VSYNC0
VSYNC1
SOGIN0
SOGIN1
COAST
HSYNC1
SERIAL REGISTER
AND
POWER MANAGEMENT
DATACK
HSOUT
VSOUT
SOGOUT
AD9888
SYNC
PROCESSING
AND CLOCK
GENERATION
CLAMP
DRA[7:0]
DRB[7:0]
DGA[7:0]
DGB[7:0]
DBA[7:0]
DBB[7:0]
ADC
CLAMP
RAIN1
RAIN0
8
8
8
ADC
CLAMP
8
8
8
ADC
CLAMP
2:1
MUX
SCL
SDA
A0
8
8
8
2
GAIN1
GAIN0
BAIN1
BAIN0
2:1
MUX
2:1
MUX
REF
BYPASS
2:1
MUX
2:1
MUX
2:1
MUX
CKINV
CKEXT
FILT
REF
Figure 1.
GENERAL DESCRIPTION
The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 170 MSPS encode rate
capability and full-power analog bandwidth of 500 MHz supports
resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.
For ease of design and to minimize cost, the AD9888 is a fully
integrated interface solution for flat panel displays. The AD9888
includes an analog interface that has a 170 MHz triple ADC with
an internal 1.25 V reference phase-locked loop (PLL) to generate a
pixel clock from HSYNC and COAST; midscale clamping; and
programmable gain, offset, and clamp controls. The user provides
only a 3.3 V power supply, analog input, and HSYNC and COAST
signals. Three-state CMOS outputs can be powered from 2.5 V
to 3.3 V.
The on-chip PLL of the AD9888 generates a pixel clock from the
HSYNC and COAST inputs. Pixel clock output frequencies
range from 10 MHz to 170 MHz. PLL clock jitter is typically
less than 450 ps p-p at 170 MSPS. When the COAST signal is
presented, the PLL maintains its output frequency in the absence of
HSYNC. A sampling phase adjustment is provided. Data, HSYNC,
and clock output phase relationships are maintained. The PLL
can be disabled, and an external clock input can be provided as
the pixel clock. The AD9888 also offers full sync processing for
composite sync and sync-on-green applications.
A CLAMP signal is generated internally or can be provided by the
user through the CLAMP input pin. This device is fully program-
mable via a 2-wire serial port.
Fabricated in an advanced CMOS process, the AD9888 is
provided in a space-saving, 128-lead, MQFP, surface-mount,
plastic package and is specified over the 0°C to 70°C temperature
range. The AD9888 is also available in a Pb-free package.


同様の部品番号 - AD9888KSZ-100

メーカー部品番号データシート部品情報
logo
Analog Devices
AD9888KS-100 AD-AD9888KS-100 Datasheet
249Kb / 32P
   100/140/170/205 MSPS Analog Flat Panel Interface
REV. A
AD9888KS-140 AD-AD9888KS-140 Datasheet
249Kb / 32P
   100/140/170/205 MSPS Analog Flat Panel Interface
REV. A
AD9888KS-170 AD-AD9888KS-170 Datasheet
249Kb / 32P
   100/140/170/205 MSPS Analog Flat Panel Interface
REV. A
AD9888KS-205 AD-AD9888KS-205 Datasheet
249Kb / 32P
   100/140/170/205 MSPS Analog Flat Panel Interface
REV. A
More results

同様の説明 - AD9888KSZ-100

メーカー部品番号データシート部品情報
logo
Analog Devices
AD9888 AD-AD9888_15 Datasheet
501Kb / 36P
   100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface
REV. C
AD9884A AD-AD9884A_15 Datasheet
220Kb / 24P
   100 MSPS/140 MSPS Analog Flat Panel Interface
REV. C
AD9884A AD-AD9884A Datasheet
186Kb / 24P
   100 MSPS/140 MSPS Analog Flat Panel Interface
REV. B
AD9884AKSZ-140 AD-AD9884AKSZ-140 Datasheet
220Kb / 24P
   100 MSPS/140 MSPS Analog Flat Panel Interface
REV. C
AD9888 AD-AD9888 Datasheet
249Kb / 32P
   100/140/170/205 MSPS Analog Flat Panel Interface
REV. A
AD9883A AD-AD9883A Datasheet
229Kb / 28P
   110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
REV. B
AD9985 AD-AD9985_15 Datasheet
355Kb / 32P
   110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
REV. 0
AD9985A AD-AD9985A Datasheet
628Kb / 32P
   110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
REV. 0
AD9985A AD-AD9985A_15 Datasheet
629Kb / 32P
   110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
REV. 0
AD9985 AD-AD9985 Datasheet
349Kb / 32P
   110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
REV. 0
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


データシート ダウンロード

Go To PDF Page


リンク URL




プライバシーポリシー
ALLDATASHEET.JP
ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com