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FM24C256FEYYX データシート(PDF) 7 Page - Fairchild Semiconductor

部品番号 FM24C256FEYYX
部品情報  256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FM24C256FEYYX データシート(HTML) 7 Page - Fairchild Semiconductor

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FM24C256 rev. B.3
Write Cycle Timing
ACKNOWLEDGE
ACK (acknowledge) is a software convention used to indicate
successful data transfers. The transmitting device, either master or
slave, will release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to
Figure 3.
The FM24C256xxx device will always respond with an acknowl-
edge after recognition of a start condition and its slave address. If
Write Cycle Timing:
SDA
SCL
STOP
CONDITION
START
CONDITION
WORD n
8th BIT
ACK
tWR
SDA
SCL
DATA STABLE
DATA
CHANGE
SDA
SCL
START CONDITION
STOP CONDITION
DS800023-4
DS800023-5
Data Validity (Figure 1)
Definition of Start and Stop (Figure 2)
DS800023-6
both the device and a WRITE operation have been selected, the
FM24C256xxx will respond with an acknowledge after the receipt
of each subsequent eight bit word.
In the READ mode the FM24C256xxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
SCL FROM
MASTER
Data Output
from Transmitter
Data Output
from Receiver
START
ACKNOWLEDGE
18
9
Acknowledge Response from Receiver (Figure 3)
DS800023-7


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