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FM24C256FLEYYX データシート(PDF) 9 Page - Fairchild Semiconductor |
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FM24C256FLEYYX データシート(HTML) 9 Page - Fairchild Semiconductor |
9 / 12 page 9 www.fairchildsemi.com FM24C256 rev. B.3 Write Protection Programming of the memory array will not take place if the WP pin is connected to VCC. The device will accept control and word addresses; but if the memory accessed is write protected by the WP pin, the FM24C256xxx will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. Read Operation Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to "1". There are three basic read operations: current address read, random read and sequential read. CURRENT ADDRESS READ Internally the FM24C256xxx contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n+1. Upon receipt of the slave address with R/W set to "1," the FM24C256xxx issues an acknowledge and transmits the eight bit word. The master will not acknowledge the transfer but does generate a stop condition, and therefore discontinues trans- mission. Refer to Figure 7 for the sequence of address, acknowl- edge and data transfer. RANDOM READ Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start condition, a slave address, and then the word address to be read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to "1". This will be followed by an acknowledge from the FM24C256xxx and then by the eight bit word. The master will not acknowledge the transfer but does generate the stop condition, and therefore the FM24C256xxx discontinues transmission. Refer to Figure 8 for the address, acknowledge, and data transfer sequence. SEQUENTIAL READ Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The FM24C256xxx continues to output data for each ac- knowledge received. The read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. The data output is sequential, with the data from address n, followed by the data n+1. The address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter "rolls over" and the FM24C256xxx continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowledge, and data transfer sequence. S T O P A C K A C K Bus Activity: Master SDA Line 101 0 0 Bus Activity A C K DATA n DATA n+63 A C K WORD ADDRESS (1) WORD ADDRESS (0) SLAVE ADDRESS S T A R T DS800023-9 Page Write (Figure 6) |
同様の部品番号 - FM24C256FLEYYX |
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同様の説明 - FM24C256FLEYYX |
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