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74AHCT595S16-13 データシート(PDF) 3 Page - Diodes Incorporated |
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74AHCT595S16-13 データシート(HTML) 3 Page - Diodes Incorporated |
3 / 10 page 74AHCT595 Document number: DS35487 Rev. 3 - 2 3 of 10 www.diodes.com June 2013 © Diodes Incorporated 74AHCT595 Functional Description and Timing Diagram Control Input Output Function SHCP STCP OE MR DS Q7S Qn X X L L L NC Low-level asserted on MR clears shift register. Storage register is unchanged X L L L L Empty shift register transferred to storage register X X H L L Z Shift register remains clear;: All Q ouputs in Z state. X L H Q6S NC HIGH is shifted into first stage of Shift Register Contents of each register shifted to next register The content of Q6S has been shifted to Q7S and now appears on device pin Q7S X L H NC QnS Contents of shift register copied to storage register. With output now in active state the storage resister contents appear on Q outputs. L H Q6S QnS Contents of shift register copied to output register then shift register shifted. H=HIGH voltage state L=LOW voltage state =LOW to HIGH transition X= don’t care – high or low (not floating) NC= No change Z= high-impedance state |
同様の部品番号 - 74AHCT595S16-13 |
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同様の説明 - 74AHCT595S16-13 |
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