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FM24CL16B-DGTR データシート(PDF) 5 Page - Cypress Semiconductor |
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FM24CL16B-DGTR データシート(HTML) 5 Page - Cypress Semiconductor |
5 / 14 page FM24CL16B - 16Kb 3V I2C F-RAM Document Number: 001-84456 Rev. *A Page 5 of 14 1 0 1 0 A2 A1 A0 R/W Slave ID Page Select Figure 4. Slave Address Word Address After the FM24CL16B (as receiver) acknowledges the slave ID, the master will place the word address on the bus for a write operation. The word address is the lower 8-bits of the address to be combined with the 3-bits of the page select to specify the exact byte to be written. The complete 11-bit address is latched internally. No word address occurs for a read operation, though the 3-bit page select is latched internally. Reads always use the lower 8-bits that are held internally in the address latch. That is, reads always begin at the address following the previous access. A random read address can be loaded by doing a write operation as explained below. After transmission of each data byte, just prior to the acknowledge, the FM24CL16B increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing. After the last address (7FFh) is reached, the address latch will roll over to 000h. There is no limit on the number of bytes that can be accessed with a single read or write operation. Data Transfer After all address information has been transmitted, data transfer between the bus master and the FM24CL16B can begin. For a read operation the device will place 8 data bits on the bus then wait for an acknowledge. If the acknowledge occurs, the next sequential byte will be transferred. If the acknowledge is not sent, the read operation is concluded. For a write operation, the FM24CL16B will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. Memory Operation The FM24CL16B is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of FRAM technology. These improvements result in some differences between the FM24CL16B and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. Write Operation All writes begin with a slave ID then a word address as previously mentioned. The bus master indicates a write operation by setting the LSB of the Slave Address to a 0. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 7FFh to 000h. Unlike other nonvolatile memory technologies, there is no write delay with FRAM. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write is complete is unnecessary and will always return a „ready‟ condition. An actual memory array write occurs after the 8 th data bit is transferred. It will be complete before the acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8 th data bit. The FM24CL16B needs no page buffering. The memory array can be write protected using the WP pin. Pulling WP high will disable writes to the entire array. The FM24CL16B will not acknowledge data bytes that are written to protected addresses. In addition, the address counter will not increment if writes are attempted to these addresses. Pulling WP low (VSS) will deactivate this feature. Figure 5 and 6 below illustrates both a single-byte and multiple-byte writes. |
同様の部品番号 - FM24CL16B-DGTR |
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同様の説明 - FM24CL16B-DGTR |
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