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FM24C64B-G データシート(PDF) 5 Page - Cypress Semiconductor

部品番号 FM24C64B-G
部品情報  64Kb Serial 5V F-RAM Memory
Download  15 Pages
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM24C64B-G データシート(HTML) 5 Page - Cypress Semiconductor

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FM24C64B
Document Number: 001-84454 Rev. *B
Page 5 of 15
1
0
1
0
A2
A1
A0 R/W
Slave
ID
Device
Select
7
6
5
4
3
2
1
0
Figure 4. Slave Address
Addressing Overview
After the FM24C64B (as receiver) acknowledges the
device address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The first is the MSB (upper byte).
Since the device uses only 13 address bits, the value
of the upper three bits are don’t care. Following the
MSB is the LSB (lower byte) with the remaining
eight address bits. The address value is latched
internally. Each access causes the latched address
value to be incremented automatically. The current
address is the value that is held in the latch, either a
newly written value or the address following the last
access. The current address will be held as long as
power remains or until a new value is written. Reads
always use the current address. A random read
address can be loaded by beginning a write operation
as explained below.
After transmission of each data byte and just prior to
the acknowledge, the FM24C64B increments the
internal address latch. This allows the next sequential
byte to be accessed with no additional addressing
externally. After the last address (1FFFh) is reached,
the address latch will roll over to 0000h. There is no
limit to the number of bytes that can be accessed with
a single read or write operation.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24C64B can begin. For a read operation, the
FM24C64B will place 8 data bits on the bus then
wait for an Acknowledge from the master. If the
Acknowledge occurs, the FM24C64B will transfer
the next sequential byte. If the Acknowledge is not
sent, the FM24C64B will end the read operation. For
a write operation, the FM24C64B will accept 8 data
bits from the master and then send an Acknowledge.
All data transfer occurs MSB (most significant bit)
first.
Memory Operation
The FM24C64B is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24C64B and a similar
configuration
EEPROM
during
writes.
The
complete operation for both writes and reads is
explained below.
Write Operation
All writes begin with a device address, then a
memory address. The bus master indicates a write
operation by setting the LSB of the device address
to a 0. After addressing, the bus master sends each
byte of data to the memory and the memory
generates an acknowledge condition. Any number of
sequential bytes may be written. If the end of the
address range is reached internally, the address
counter will wrap from 1FFFh to 0000h.
Unlike other nonvolatile memory technologies,
there is no write delay with FRAM. The entire
memory cycle occurs in less time than a single bus
clock. Therefore, any operation including a read or
write can occur immediately following a write.
Acknowledge
polling,
a
technique
used
with
EEPROMs to determine if a write is complete is
unnecessary and
will
always
return a
ready
condition.
Internally, the actual memory write occurs after the
8
th data bit is transferred. It will be complete before
the Acknowledge is sent. Therefore, if the user
desires to abort a write without altering the memory
contents, this should be done using a Start or Stop
condition prior to the 8
th data bit. The FM24C64B
uses no page buffering.
The memory array can be write protected using the
WP pin. Pulling the WP pin high will write-protect
the
entire
array.
The
FM24C64B
will
not
acknowledge data bytes that are written to protected
addresses. In addition, the address counter will not
increment if writes are attempted. Pulling WP low
(VSS) will deactivate this feature.
Figures 5 and 6 illustrate both a single-byte and
multiple-byte write cases.


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