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FM24C64B-GTR データシート(PDF) 2 Page - Cypress Semiconductor

部品番号 FM24C64B-GTR
部品情報  64Kb Serial 5V F-RAM Memory
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

FM24C64B-GTR データシート(HTML) 2 Page - Cypress Semiconductor

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FM24C64B
Document Number: 001-84454 Rev. *B
Page 2 of 15
Address
Latch
1,024 x 64
FRAM Array
8
SDA
Counter
Serial to Parallel
Converter
Control Logic
SCL
WP
A0-A2
Data Latch
Figure 1. FM24C64B Block Diagram
Pin Description
Pin Name
I/O
Pin Description
A0-A2
Input
Address 2-0: These pins are used to select one of up to 8 devices of the same type on
the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.
SDA
I/O
Serial Data Address: This is a bi-directional pin used to shift serial data and addresses
for the two-wire interface. It employs an open-drain output and is intended to be wire-
OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt
trigger for noise immunity and the output driver includes slope control for falling
edges. A pull-up resistor is required.
SCL
Input
Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of
the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL
input also incorporates a Schmitt trigger input for improved noise immunity.
WP
Input
Write Protect: When WP is high, the entire array is write-protected. When WP is low,
all addresses may be written. This pin is pulled down internally.
VDD
Supply
Supply Voltage: 5V
VSS
Supply
Ground


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