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DAC088S085 データシート(PDF) 3 Page - Texas Instruments |
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DAC088S085 データシート(HTML) 3 Page - Texas Instruments |
3 / 35 page 1 2 3 4 13 14 15 SCLK DAC088S085 SYNC VOUTA 16 5 6 7 8 VA 9 10 11 VOUTG 12 VOUTB VOUTC VOUTD VREF1 VOUTF VOUTH VOUTE GND VREF2 DIN DOUT 1 2 3 4 DAC088S085 VOUTA VOUTB VOUTC VOUTD 9 10 11 VOUTG 12 VOUTF VOUTH VOUTE DAC088S085 www.ti.com SNAS424C – AUGUST 2007 – REVISED MARCH 2013 Pin Configurations WQFN TSSOP PIN DESCRIPTIONS WQFN TSSOP Symbol Type Description Pin No. Pin No. 1 3 VOUTA Analog Output Channel A Analog Output Voltage. 2 4 VOUTB Analog Output Channel B Analog Output Voltage. 3 5 VOUTC Analog Output Channel C Analog Output Voltage. 4 6 VOUTD Analog Output Channel D Analog Output Voltage. 5 7 VA Supply Power supply input. Must be decoupled to GND. Unbuffered reference voltage shared by Channels A, B, C, and D. 6 8 VREF1 Analog Input Must be decoupled to GND. Unbuffered reference voltage shared by Channels E, F, G, and H. 7 9 VREF2 Analog Input Must be decoupled to GND. 8 10 GND Ground Ground reference for all on-chip circuitry. 9 11 VOUTH Analog Output Channel H Analog Output Voltage. 10 12 VOUTG Analog Output Channel G Analog Output Voltage. 11 13 VOUTF Analog Output Channel F Analog Output Voltage. 12 14 VOUTE Analog Output Channel E Analog Output Voltage. Frame Synchronization Input. When this pin goes low, data is written into the DAC's input shift register on the falling edges of SCLK. After the 16th falling edge of SCLK, a rising edge of SYNC causes the 13 15 SYNC Digital Input DAC to be updated. If SYNC is brought high before the 15th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the 14 16 SCLK Digital Input falling edges of this pin. Serial Data Input. Data is clocked into the 16-bit shift register on the 15 1 DIN Digital Input falling edges of SCLK after the fall of SYNC. Serial Data Output. DOUT is utilized in daisy chain operation and is connected directly to a DIN pin on another DAC088S085. Data is not 16 2 DOUT Digital Output available at DOUT unless SYNC remains low for more than 16 SCLK cycles. Exposed die attach pad can be connected to ground or left floating. PAD 17 Ground Soldering the pad to the PCB offers optimal thermal performance (LLP only) and enhances package self-alignment during reflow. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DAC088S085 |
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同様の説明 - DAC088S085 |
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