DAC2932

SBAS279D − AUGUST 2003 − REVISED JULY 2005

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8

PIN ASSIGNMENTS

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44 43 42 41 40 39 38

13 14 15 16 17 18 19 20 21 22 23

37

24

DAC2932

(V−DAC Section)

NC

AGND

AGND

AGND

D11 (MSB)

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0 (LSB)

Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

D11:D0

1:12

I

Parallel data input port for the dual I-DACs; MSB = D11, LSB = D0; interleaved operation.

DGND

13

Digital ground of I-DAC

+VD

14

Digital supply of I-DAC; 2.7V to 3.3V

CLK

15

I

Clock input of I-DAC

PD

16

I

Power-down pin; active high; a logic high initiates power-down mode.

STBY

17

I

Standby pin of I-DAC; active low; a logic low initiates Standby mode with PD = Low.

A logic high configures the I-DAC for normal operation; pin will resume a high state if left open.

CS

18

I

Chip select; active low; enables the parallel data port of the I−DACs; if used as chip select in applications

using multiple DAC2932 devices, the parallel port data must be scrambled for proper functionality. Pin will

resume a low state if left open.

GSET

19

I

Gain-setting mode. A logic high enables the use of two separate full-scale adjust resistors on pins FSA1

and FSA2. A logic low allows the use of a common full-scale adjust resistor connected to FSA1. The

function of the FSA2 pin is disabled, and any remaining resistor has no effect. The value for the RSET

resistor remains the same for a given full-scale range, regardless of the selected GSET mode. Pin will

resume a low state if left open.

DGND

20

Digital ground of I-DAC

AGND

21

Analog ground of I-DAC

AGND

22

Analog ground of I-DAC

FSA2

23

I

Full-scale adjust of I-DAC2; connect external gain setting resistor RSET2 = 19.6kΩ.

FSA1

24

I

Full-scale adjust of I-DAC1; connect external gain setting resistor RSET1 = 19.6kΩ.