データシートサーチシステム |
|
CS1W-NC133 データシート(PDF) 3 Page - Omron Electronics LLC |
|
CS1W-NC133 データシート(HTML) 3 Page - Omron Electronics LLC |
3 / 70 page The CS1 provides a high level of space efficiency. As many as 960 I/O points can be controlled by simply mounting ten Basic I/O Units, with 96 I/O points each, to the CPU Rack. Alternatively, as many as 80 analog I/O points can be used by mounting five Analog Input Units and five Analog Output Units. Wide Lineup Makes It Easy to Build the Optimum System Large Capacity CPU Units for Greater Component Control Power Two Series of Expansion Racks Up to 50 m Long for Long-distance Expansion with Up to 72 Units and 7 Racks Control Up to 960 Points with Units Mounted to the CPU Rack Use the improved SYSMAC CS1 PLCs to scale advanced systems to the optimum size. 11 With an expansion capacity of up to 80 Units and 7 Racks over a distance of 12 meters, the CS1 can meet large-scale control needs. Alternatively, an I/O Control Unit and I/O Interface Units can be used to connect two series of CS1 Longdistance Expansion Racks extending up to 50 m each and containing a total of up to 72 Units and 7 Racks. CS1 Basic I/O Units, CS1 Special I/O Units, and CS1 CPU Bus Units can be mounted anywhere on the Racks and programmed without being concerned about special remote programming requirements. Note: C200H Units cannot be mounted on the Longdistance Expansion Racks. The CS1 CPU Units boast amazing capacity with up to 5,120 I/O points, 250 Ksteps of programming, 448 Kwords of data memory (including expanded data memory) and 4,096 timers/counters each. With a large programming capacity, CS1 PLCs are not only ideal for large-scale systems but easily handle value-added applications and other advanced data processing. A total of nine CPU Unit models provide for a wide range of applications, from small-scale systems to large. The lineup also includes Memory Cards, Serial Communications Boards, and a wide selection of Special I/O Units that can be used with any CPU Units to flexibly build the system that meets the requirements. 0.3 ms Ten I/O Units of 96 points each Five Analog Output Units of 8 points each Five Analog Input Units of 8 points each 9 Units Terminating Resistor 50 m 50 m I/O Interface Unit I/O Control Unit CPU 2 Series of Expansion Racks; Up to 7 Racks Total Program Capacity 250 K steps 120 K steps 60 K steps 30 K steps 20 K steps 10 K steps Product lineup (Example: LD instruction processing speed, DM capacity) Number of I/O points 960 pts 1,280 pts 5,120 pts Faster Instruction Execution and Faster Overall Performance In addition to further improvements to the instruction execution engine, which is the core of overall PLC performance, the high-speed RISC chip has been upgraded to realize the fastest instruction execution performance in the industry. Also, the new models have a mode where instruction execution and peripheral processing are processed in parallel, enabling balanced improvements in overall speed. ● Common Processing ● PCMIX Value ● LD Instruction Processing Speed ● Cycle Time ( ) ● OUT Instruction Processing Speed ● Subroutine Processing Speed 16 20 ns 20 ns 2.1 µs Basic instructions only: 38 Ksteps/ms Including special instructions: 22 Ksteps/ms Cycle time for 128 inputs and 128 outputs The data transfer rate between the CPU Unit and certain Units has been doubled to further improve total system performance. Special I/O Unit CPU Unit System bus Baud rate doubled CPU Unit CPU Bus Unit n DLNK n ● CIO Area words allocated to CPU Bus Units ● DM Area words allocated for CPU Bus Units ● Specific Area for CPU Bus Units Controller Link Unit DeviceNet Unit Serial Communications Unit Ethernet Unit Data links Remote I/O Protocol macros Socket service based on manipulation of specific bits. Immediate I/O refresh Refresh function Unit name Data exchange during communications cycle System Bus Baud Rate Doubled Table data/ text string processing Long execution time The cycle is temporarily extended when the instruction is executed. Variation Background processing performed over several cycles to limit the impact on cycle time and thus reduce variation in cycle time. Only start of processing designated. Reduced Variation in Cycle Time During Data Processing Instructions that require long execution time, such as table data processing instructions and text string processing instructions, are processed over multiple cycles to minimize variations in cycle time and maintain stable I/O response. Improved Refresh Performance for Data Links, Remote I/O Communications, and Protocol Macros In the past, I/O refresh processing with the CPU Bus Unit only occurred during I/O refresh after instructions were executed. With the new CS1, however, I/O can be refreshed immediately by using the DLNK instruction. Immediate refreshing for processes peculiar to the CPU Bus Unit, such as for data links and DeviceNet remote I/O communications, and for allocated CIO Area/DM Area words when instructions are executed, means greater refresh responsiveness for CPU Bus Units. F-4 F-5 Table data/ text string processing (LD: 0.02 µs, DM: 448 Kwords) (LD: 0.02 µs, DM: 256 Kwords) (LD: 0.02 µs, DM: 128 Kwords) (LD: 0.04 µs, DM: 128 Kwords) (LD: 0.04 µs, DM: 64 Kwords) (LD: 0.02 µs, DM: 64 Kwords) (LD: 0.02 µs, DM: 64 Kwords) (LD: 0.04 µs, DM: 64 Kwords) (LD: 0.04 µs, DM: 64 Kwords) |
同様の部品番号 - CS1W-NC133 |
|
同様の説明 - CS1W-NC133 |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |