FSTUD162450MTD datasheet(7/11 Pages) FAIRCHILD

部品番号	FSTUD162450MTD

部品情報	Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting and 25??Series Resistors in Outputs

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メーカー	FAIRCHILD [Fairchild Semiconductor]

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AC Electrical Characteristics

Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On

Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).

AC Electrical Characteristics: Translating Diode

Note 9: This parameter is guaranteed by design but is not tested. This bus switch contributes no propagation delay other than the RC delay of the typical On

Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).

Capacitance (Note 10)

Note 10: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.

Symbol

Parameter

TA = −40 °C to +85 °C,

Units

CL = 50pF, RU = RD = 500Ω

Conditions

Figure

VCC = 4.5 – 5.5V

VCC = 4.0V

(S2 = 0V)

Number

Min

Max

Min

Max

tPHL, tPLH

Propagation Delay Bus-to-Bus

(Note 8)

1.25

ns

VI = OPEN

Figures

2, 3

tPZH, tPZL

Output Enable Time

1.5

7.5

8.0

ns

VI = 7V for tPZL

Figures

2, 3

VI = OPEN for tPZH

tPHZ, tPLZ

Output Disable Time

1.5

7.7

8.2

ns

VI = 7V for tPLZ

Figures

2, 3

VI = OPEN for tPHZ

tPZH, tPZL

Sel (S0, 1) to Output Enable Time

1.5

8.0

8.5

ns

VI = 7V for tPZL

Figures

2, 3

VI = OPEN for tPZH

tPHZ, tPLZ

Sel (S0, 1) to Output Disable Time

1.5

8.5

8.7

ns

VI = 7V for tPLZ

Figures

2, 3

VI = OPEN for tPHZ

Symbol

Parameter

TA = −40 °C to +85 °C,

Units

CL = 50pF, RU = RD = 500Ω

Conditions

Figure

VCC = 4.5 – 5.5V

(S2 = VCC)

Number

Min

Max

tPHL, tPLH

Propagation Delay Bus-to-Bus (Note 9)

1.25

ns

VI = OPEN

Figures

2, 3

tPZH, tPZL

Output Enable Time

1.5

10.0

ns

VI = 7V for tPZL

Figures

2, 3

VI = OPEN for tPZH

tPHZ, tPLZ

Output Disable Time

1.5

9.0

ns

VI = 7V for tPLZ

Figures

2, 3

VI = OPEN for tPHZ

tPZH, tPZL

Sel (S0, 1) to Output Enable Time

1.5

11.0

ns

VI = 7V for tPZL

Figures

2, 3

VI = OPEN for tPZH

tPHZ, tPLZ

Sel (S0, 1) to Output Disable Time

1.5

10.0

ns

VI = 7V for tPLZ

Figures

2, 3

VI = OPEN for tPHZ

Symbol

Parameter

Typ

Max

Units

Conditions

CIN

Control Pin Input Capacitance

3.5

pF

VCC = 5.0V, VIN = 0V

CI/O

Input/Output Capacitance “OFF State”

6pF

VCC, OE = 5.0V, VIN = 0V

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