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AD9106 データシート(PDF) 6 Page - Analog Devices |
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AD9106 データシート(HTML) 6 Page - Analog Devices |
6 / 48 page AD9106 Data Sheet Rev. A | Page 6 of 48 DIGITAL TIMING SPECIFICATIONS (3.3 V) TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate, unless otherwise noted. Table 3. Parameter Min Typ Max Unit DAC CLOCK INPUT (CLKIN) Maximum Clock Rate 180 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 80 MHz Minimum Pulse Width High 6.25 ns Minimum Pulse Width Low 6.25 ns Setup Time SDIO to SCLK 4.0 ns Hold Time SDIO to SCLK 5.0 ns Output Data Valid SCLK to SDO or SDIO 6.2 ns Setup Time EE AA to SCLK CS 4.0 ns DIGITAL TIMING SPECIFICATIONS (1.8 V) TMIN to TMAX, AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V, IOUTFS = 4 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter Min Typ Max Unit DAC CLOCK INPUT (CLKIN) Maximum Clock Rate 180 MSPS SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) 80 MHz Minimum Pulse Width High 6.25 ns Minimum Pulse Width Low 6.25 ns Setup Time SDIO to SCLK 4.0 ns Hold Time SDIO to SCLK 5.0 ns Output Data Valid SCLK to SDO or SDIO 8.8 ns Setup Time AA CSEE AA to SCLK 4.0 ns |
同様の部品番号 - AD9106 |
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同様の説明 - AD9106 |
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