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LM3279 データシート(PDF) 3 Page - Texas Instruments |
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LM3279 データシート(HTML) 3 Page - Texas Instruments |
3 / 31 page Top View (Bumps Down) SCLK GPO0 GND VOUT SDATA VCON VIO FB GPO1 SW2 EN SGND SVIN PGND PVIN SW1 A B C D 1 2 3 4 LM3279 www.ti.com SNVS970A – MARCH 2013 – REVISED MAY 2013 CONNECTION DIAGRAM Figure 1. 16-Bump Thin DSBGA Package, Large Bump PIN DESCRIPTIONS Pin # Name Description Digital control interface (DCON) RFFE Bus clock input. Typically connected to RFFE master on RF or A1 SCLK Baseband IC. SCLK must be held low when VIO is not applied. Digital control interface (DCON) RFFE Bus data input/output. Typically connected to RFFE master on RF B1 SDATA or Baseband IC. SDATA must be held low when VIO is not applied. Digital control interface (DCON) 1.8V supply input. VIO functions as the RFFE interface reference voltage. VIO also functions as a reset and enable input to LM3279. Bypass capacitor should be C1 VIO connected between VIO and GND. Typically connected to voltage regulator controlled by RF or Baseband IC. When VIO = HIGH, EN shall be connected to GND. D1 GND Digital Ground. Multipurpose GPIO. When VIO = HIGH, GPO0 is a general purpose output for configuring RF front end circuitry. When the GPO0 control bit in Register 02 is set to 1, the output is driven to a 1.8V (VIO) high A2 GPO0 logic level. The output is pulled to a low logic level when the GPO0 control bit is set to 0. (Input has an internal pullup resistor.) Voltage Control Analog input. When EN = HIGH, VCON controls the output voltage in PWM and PFM B2 VCON modes. When in Digital control, VCON can be left as no connect or connected to system ground. Feedback input to inverting input of error amplifier. Connect output voltage directly to this node at load C2 FB point. D2 VOUT Regulated output voltage of LM3279. Connect this to a 10 µF ceramic output filter capacitor to GND. Multipurpose GPIO. When VIO = HIGH, GPO1 is a general purpose output for configuring RF front end circuitry. When the GPO1 control bit in Register 02 is set to 1, the output is driven to a 1.8V (VIO) high A3 GPO1 logic level. The output is pulled to a low logic level when the GPO1 control bit is set to 0. (Input has an internal pullup resistor.) Enable Pin. Pulling this pin higher than 1.2V enables part to function in analog control mode. VIO must be B3 EN tied to ground. C3 SGND Signal Ground for analog circuits and control circuitry. D3 SW2 Switch pin for Internal Power Switches M3 and M4. Connect inductor between SW1 and SW2. A4 SVIN SVIN is no connect. Analog supply is internally connected to PVIN. Power MOSFET input and power current input pin. Optional low-pass filtering may help reduce radiated B4 PVIN EMI and noise during buck and buck-boost modes. C4 SW1 Switch pin for Internal Power Switches M1 and M2. Connect inductor between SW1 and SW2. D4 PGND Power Ground for Power MOSFETs and gate drive circuitry. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM3279 |
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同様の説明 - LM3279 |
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