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TL16C754BPNRG4 データシート(PDF) 4 Page - Texas Instruments

部品番号 TL16C754BPNRG4
部品情報  QUAD UART WITH 64-BYTE FIFO
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TL16C754BPNRG4 データシート(HTML) 4 Page - Texas Instruments

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TL16C754B
QUAD UART WITH 64BYTE FIFO
SLLS397A − NOVEMBER 1999 − REVISED JUNE 2004
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
NAME
PN
FN
I/O
DESCRIPTION
RESET
33
37
I
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output
and the receiver input will be disabled during reset time. See TL16C754B external reset
conditions for initialization details. RESET is an active high input.
RIA, RIB
RIC, RID
78, 24
38, 64
8, 28
42, 62
I
Ring indicator (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates the modem has received a ringing signal from the telephone line.
A low to high transition on these input pins generates a modem status interrupt, if it is enabled.
RTSA, RTSB
RTSC, RTSD
7, 15
47, 55
14, 22
48, 56
O
Request to send (active low). These outputs are associated with individual UART channels A
through D. A low on the RTS pins indicates the transmitter has data ready and waiting to send.
Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is
available. After a reset, these pins are set to 1. These pins only affects the transmit and receive
operation when auto RTS function is enabled through the enhanced feature register (EFR) bit 6,
for hardware flow control operation.
RXA, RXB
RXC, RXD
77, 25
37, 65
7, 29
41, 63
I
Receive data input. These inputs are associated with individual serial channel data to the 754A.
During the local loopback mode, these RX input pins are disabled and TX data is internally
connected to the UART RX input internally.
RXRDY
34
38
O
Receive ready (active low). RXRDY contains the wire-ORed status of all four receive channel
FIFOs, RXRDY A−D. It goes low when the trigger level has been reached or a timeout interrupt
occurs. It goes high when all RX FIFOs are empty and there is an error in RX FIFO.
TXA, TXB
TXC, TXD
10, 12
50, 52
17, 19
51, 53
O
Transmit data. These outputs are associated with individual serial transmit channel data from the
754A. During the local loopback mode, the TX input pin is disabled and TX data is internally
connected to the UART RX input.
TXRDY
35
39
O
Transmit ready (active low). TXRDY contains the wire-ORed status of all four transmit channel
FIFOs, TXRDY A−D. It goes low when there are a trigger level number of spares available. It goes
high when all four TX buffers are full.
VCC
6, 46,
66
13, 47,
64
Pwr
Power supply inputs
XTAL1
31
35
I
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input.
A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figure 10). Alternatively, an external clock can be connected to XTAL1 to provide custom data
rates.
XTAL2
32
36
O
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
oscillator output or buffered clock output.


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