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AD5339BRMZ-REEL データシート(PDF) 6 Page - Analog Devices

部品番号 AD5339BRMZ-REEL
部品情報  2.5 V to 5.5 V, 250 muA, 2-Wire Interface
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD5339BRMZ-REEL データシート(HTML) 6 Page - Analog Devices

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AD5337/AD5338/AD5339
Rev. C | Page 6 of 28
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
Parameter
A Version and B Version
Unit
Conditions/Comments
fSCL
400
kHz max
SCL clock frequency
t1
2.5
μs min
SCL cycle time
t2
0.6
μs min
tHIGH, SCL high time
t3
1.3
μs min
tLOW, SCL low time
t4
0.6
μs min
tHD, STA, start/repeated start condition hold time
t5
100
ns min
tSU, DAT, data setup time
t61
0.9
μs max
tHD, DAT, data hold time
0
μs min
tHD, DAT, data hold time
t7
0.6
μs min
tSU, STA, setup time for repeated start
t8
0.6
μs min
tSU, STO, stop condition setup time
t9
1.3
μs min
tBUF, bus free time between a stop and a start condition
t10
300
ns max
tR, rise time of SCL and SDA when receiving
0
ns min
tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11
250
ns max
tF, fall time of SDA when transmitting
0
ns min
tF, fall time of SDA when receiving (CMOS compatible)
300
ns max
tF, fall time of SCL and SDA when receiving
20 + 0.1 CB2
ns min
tF, fall time of SCL and SDA when transmitting
CB
400
pF max
Capacitive load for each bus line
1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
2 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 VDD and 0.7 VDD.
t9
t3
t4
t6
t2
t5
t7
t8
t1
t4
t11
t10
SDA
SCL
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram


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