AD9920ABBCZ datasheet(98/112 Pages) AD

部品番号	AD9920ABBCZ

部品情報	12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator

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AD9920A

Rev. B | Page 98 of 112

Table 54. VD/HD Registers

Address

Data Bits

Default Value

Default

Update Type

Name

Description

0x20

[0]

0

SCK

MASTER

VD/HD master or slave mode. 0 = slave mode, 1 = master mode.

0x21

[0]

0

VD

VDHDPOL

VD/HD active polarity. 0 = low, 1 = high.

0x22

[12:0]

0

VD

HDRISE

Rising edge location for HD. Minimum value is 36 pixels.

[25:13]

0

VDRISE

Rising edge location for VD.

Table 55. I/O Registers

Address

Data

Bits

Default

Value

Default

Update

Type

Name

Description

0x23

[0]

0

SCK

OSC_NVR

Oscillator normal voltage range. Set to match CLIVDD supply voltage.

0 = 1.8 V.

1 = 3.3 V.

[1]

0

XV_NVR

XV output normal voltage range. Set to match VDVDD supply voltage.

0 = 1.8 V.

1 = 3.3 V.

[2]

0

IO_NVR

I/O normal voltage range. Set to match IOVDD supply voltage.

0 = 1.8 V.

1 = 3.3 V.

[3]

0

DATA_NVR

Data pin normal voltage range. Set to match DRVDD supply voltage.

0 = 1.8 V I/O.

1 = 3.3 V I/O.

[4]

0

Test

Test use only. Set to 0.

[5]

0

Test

Test use only. Set to 0.

[6]

0

Test

Test use only. Set to 0.

0x24

[4:0]

0x01

SCK

HCLKMODE

Selects HCLK output configuration. Should be written to desired value.

Note that all other settings are invalid.

0x01 = Mode 1.

0x02 = Mode 2.

0x04 = Mode 3.

0x10 = 3-phase HCLK mode.

[5]

0

Test

Test use only. Set to 0.

0x25

[24:0]

0

SCK

VT_STBY12

Bits[23:0]: Standby1 and Standby2 polarity for XV[23:0].

Bit 24: Standby1 and Standby2 polarity for XSUBCK.

Settings also apply when OUT_CONTROL = low.

0x26

[24:0]

0

SCK

VT_STBY3

Bits[23:0]: Standby3 polarity for XV[23:0].

Bit 24: Standby3 polarity for XSUBCK.

0x27

[7:0]

0

SCK

GP_STDBY12

Standby1 and Standby2 polarity for GPO outputs.

Settings also apply when OUT_CONTROL = low.

[15:8]

0

GP_STDBY3

Standby3 polarity for GPO outputs.

Table 56. Memory Configuration and Mode Registers

Address

Data Bits

Default Value

Update Type

Name

Description

0x28

[4:0]

0

SCK

VPATNUM

Total number of V-pattern groups.

[9:5]

0

SEQNUM

Total number of V-sequences.

0x29

[27]

0

SCK

UNUSED

Do not access, or set to 0.

0x2A

[2:0]

0

SCK

Mode

Total number of fields in the mode register.

0x2B

[4:0]

0

SCK

FIELD1

Selected first field in the mode register.

[9:5]

0

FIELD2

Selected second field in the mode register.

[14:10]

0

FIELD3

Selected third field in the mode register.

[19:15]

0

FIELD4

Selected fourth field in the mode register.

[24:20]

0

FIELD5

Selected fifth field in the mode register.

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同様の説明 - AD9920ABBCZ

メーカー	部品番号	データシート	部品情報
Analog Devices	AD9920A	73Kb / 2P	12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator Rev. Sp0
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	AD9995	2Mb / 60P	12-Bit CCD Signal Processor with Precision Timing Generator REV. 0
	AD9923A	1Mb / 84P	CCD Signal Processor with V-Driver and Precision Timing Generator REV. A
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