AD9920ABBCZRL datasheet(27/112 Pages) AD

部品番号	AD9920ABBCZRL

部品情報	12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator

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AD9920A

Rev. B | Page 27 of 112

Register

Length

(Bits)

Range

Description

HBLKSTARTA

13

0 to 8191 pixel location

HBLK Repeat Area Start Position A for HBLK Mode 1. Set to 8191 if not used.

HBLKSTARTB

13

0 to 8191 pixel location

HBLK Repeat Area Start Position B for HBLK Mode 1. Set to 8191 if not used.

HBLKSTARTC

13

0 to 8191 pixel location

HBLK Repeat Area Start Position C for HBLK Mode 1. Set to 8191 if not used.

HBLKALT_PAT0

3

0 to 5 even repeat area

HBLK Mode 1, Repeat Area 0 pattern for odd lines. Selected from previously

defined even line repeat areas.

HBLKALT_PAT1

3

0 to 5 even repeat area

HBLK Mode 1, Repeat Area 1 pattern for odd lines.

HBLKALT_PAT2

3

0 to 5 even repeat area

HBLK Mode 1, Repeat Area 2 pattern for odd lines.

HBLKALT_PAT3

3

0 to 5 even repeat area

HBLK Mode 1, Repeat Area 3 pattern for odd lines.

HBLKALT_PAT4

3

0 to 5 even repeat area

HBLK Mode 1, Repeat Area 4 pattern for odd lines.

HBLKALT_PAT5

3

0 to 5 even repeat area

HBLK Mode 1, Repeat Area 5 pattern for odd lines.

1 PIXEL

MASK LEVEL = HIGH

MASK LEVEL = LOW

BLANKING

PHASE 1

PHASE 3

PHASE 2

INTERNAL

DIGITAL

CLOCK

MASTER

BLANKING

SIGNAL

H1/H2

H5/H6

H7/H8

1 PIXEL

A3

A2

A1

A

B

B3

B2

B1

Figure 33. Example of Correct HBLK Behavior

HBLK Fine Retime Control

Figure 33 shows the desired HBLK behavior for all three phases

when the internal digital clock is located before the Phase 3 rising

edge. Figure 34 shows the effect of changing the internal clock

phase (changing SHDLOC) to a different location. This causes

incorrect blanking on Phase 1 and Phase 2.

An additional set of register bits is available for use during

3-phase HCLK mode to provide fine adjustment of each HCLK

phase during the HBLK interval. The fine retime bits (Address 0x35,

Bits[23:20]) allow for the adjustment of the correct number of

HCLK cycles during the HBLK interval.

Figure 35 shows how the fine retime bits for Phase 1 and Phase 2

are used to generate the correct blanking behavior, matching the

result shown in Figure 33.

Figure 33 through Figure 35 show the different settings that can

be used based on the location of the HBLK toggle positions, the

location of the internal digital clock, and the masking polarity

of the different HCLK phases. By using the fine retime bits, the

exact pulse behavior for each HCLK phase can be generated.

同様の部品番号 - AD9920ABBCZRL

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同様の説明 - AD9920ABBCZRL

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Analog Devices	AD9920A	73Kb / 2P	12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator Rev. Sp0
	AD9920A	1Mb / 112P	12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator REV. B
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